/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* mace.h - definitions for the registers in the "Big Mac"
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* Ethernet controller found in PowerMac G3 models.
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*
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* Copyright (C) 1998 Randy Gobbel.
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*/
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/* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal"
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* (HME) controller. See sunhme.h
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*/
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/* register offsets */
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/* global status and control */
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#define XIFC 0x000 /* low-level interface control */
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# define TxOutputEnable 0x0001 /* output driver enable */
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# define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
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# define MIILoopback 0x0004 /* Loopback-mode MII enable */
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# define MIILoopbackBits 0x0006
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# define MIIBuffDisable 0x0008 /* MII receive buffer disable */
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# define SQETestEnable 0x0010 /* SQE test enable */
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# define SQETimeWindow 0x03e0 /* SQE time window */
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# define XIFLanceMode 0x0010 /* Lance mode enable */
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# define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
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#define TXFIFOCSR 0x100 /* transmit FIFO control */
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# define TxFIFOEnable 0x0001
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#define TXTH 0x110 /* transmit threshold */
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# define TxThreshold 0x0004
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#define RXFIFOCSR 0x120 /* receive FIFO control */
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# define RxFIFOEnable 0x0001
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#define MEMADD 0x130 /* memory address, unknown function */
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#define MEMDATAHI 0x140 /* memory data high, presently unused in driver */
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#define MEMDATALO 0x150 /* memory data low, presently unused in driver */
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#define XCVRIF 0x160 /* transceiver interface control */
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# define COLActiveLow 0x0002
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# define SerialMode 0x0004
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# define ClkBit 0x0008
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# define LinkStatus 0x0100
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#define CHIPID 0x170 /* chip ID */
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#define MIFCSR 0x180 /* ??? */
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#define SROMCSR 0x190 /* SROM control */
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# define ChipSelect 0x0001
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# define Clk 0x0002
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#define TXPNTR 0x1a0 /* transmit pointer */
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#define RXPNTR 0x1b0 /* receive pointer */
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#define STATUS 0x200 /* status--reading this clears it */
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#define INTDISABLE 0x210 /* interrupt enable/disable control */
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/* bits below are the same in both STATUS and INTDISABLE registers */
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# define FrameReceived 0x00000001 /* Received a frame */
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# define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
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# define RxAlignCntExp 0x00000004 /* Align-error counter expired */
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# define RxCRCCntExp 0x00000008 /* CRC-error counter expired */
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# define RxLenCntExp 0x00000010 /* Length-error counter expired */
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# define RxOverFlow 0x00000020 /* Receive FIFO overflow */
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# define RxCodeViolation 0x00000040 /* Code-violation counter expired */
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# define SQETestError 0x00000080 /* Test error in XIF for SQE */
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# define FrameSent 0x00000100 /* Transmitted a frame */
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# define TxUnderrun 0x00000200 /* Transmit FIFO underrun */
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# define TxMaxSizeError 0x00000400 /* Max-packet size error */
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# define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */
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# define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */
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# define TxLateCollExp 0x00002000 /* Late-collision counter expired */
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# define TxNetworkCollExp 0x00004000 /* First-collision counter expired */
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# define TxDeferTimerExp 0x00008000 /* Defer-timer expired */
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# define RxFIFOToHost 0x00010000 /* Data moved from FIFO to host */
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# define RxNoDescriptors 0x00020000 /* No more receive descriptors */
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# define RxDMAError 0x00040000 /* Error during receive DMA */
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# define RxDMALateErr 0x00080000 /* Receive DMA, data late */
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# define RxParityErr 0x00100000 /* Parity error during receive DMA */
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# define RxTagError 0x00200000 /* Tag error during receive DMA */
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# define TxEOPError 0x00400000 /* Tx descriptor did not have EOP set */
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# define MIFIntrEvent 0x00800000 /* MIF is signaling an interrupt */
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# define TxHostToFIFO 0x01000000 /* Data moved from host to FIFO */
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# define TxFIFOAllSent 0x02000000 /* Transmitted all packets in FIFO */
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# define TxDMAError 0x04000000 /* Error during transmit DMA */
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# define TxDMALateError 0x08000000 /* Late error during transmit DMA */
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# define TxParityError 0x10000000 /* Parity error during transmit DMA */
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# define TxTagError 0x20000000 /* Tag error during transmit DMA */
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# define PIOError 0x40000000 /* PIO access got an error */
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# define PIOParityError 0x80000000 /* PIO access got a parity error */
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# define DisableAll 0xffffffff
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# define EnableAll 0x00000000
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/* # define NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */
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# define EnableNormal ~(FrameReceived | FrameSent)
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# define EnableErrors (FrameReceived | FrameSent)
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# define RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \
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RxLenCntExp | RxOverFlow | RxCodeViolation)
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# define TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \
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TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp)
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/* transmit control */
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#define TXRST 0x420 /* transmit reset */
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# define TxResetBit 0x0001
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#define TXCFG 0x430 /* transmit configuration control*/
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# define TxMACEnable 0x0001 /* output driver enable */
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# define TxSlowMode 0x0020 /* enable slow mode */
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# define TxIgnoreColl 0x0040 /* ignore transmit collisions */
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# define TxNoFCS 0x0080 /* do not emit FCS */
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# define TxNoBackoff 0x0100 /* no backoff in case of collisions */
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# define TxFullDuplex 0x0200 /* enable full-duplex */
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# define TxNeverGiveUp 0x0400 /* don't give up on transmits */
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#define IPG1 0x440 /* Inter-packet gap 1 */
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#define IPG2 0x450 /* Inter-packet gap 2 */
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#define ALIMIT 0x460 /* Transmit attempt limit */
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#define SLOT 0x470 /* Transmit slot time */
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#define PALEN 0x480 /* Size of transmit preamble */
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#define PAPAT 0x490 /* Pattern for transmit preamble */
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#define TXSFD 0x4a0 /* Transmit frame delimiter */
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#define JAM 0x4b0 /* Jam size */
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#define TXMAX 0x4c0 /* Transmit max pkt size */
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#define TXMIN 0x4d0 /* Transmit min pkt size */
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#define PAREG 0x4e0 /* Count of transmit peak attempts */
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#define DCNT 0x4f0 /* Transmit defer timer */
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#define NCCNT 0x500 /* Transmit normal-collision counter */
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#define NTCNT 0x510 /* Transmit first-collision counter */
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#define EXCNT 0x520 /* Transmit excess-collision counter */
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#define LTCNT 0x530 /* Transmit late-collision counter */
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#define RSEED 0x540 /* Transmit random number seed */
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#define TXSM 0x550 /* Transmit state machine */
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/* receive control */
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#define RXRST 0x620 /* receive reset */
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# define RxResetValue 0x0000
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#define RXCFG 0x630 /* receive configuration control */
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# define RxMACEnable 0x0001 /* receiver overall enable */
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# define RxCFGReserved 0x0004
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# define RxPadStripEnab 0x0020 /* enable pad byte stripping */
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# define RxPromiscEnable 0x0040 /* turn on promiscuous mode */
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# define RxNoErrCheck 0x0080 /* disable receive error checking */
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# define RxCRCNoStrip 0x0100 /* disable auto-CRC-stripping */
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# define RxRejectOwnPackets 0x0200 /* don't receive our own packets */
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# define RxGrpPromisck 0x0400 /* enable group promiscuous mode */
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# define RxHashFilterEnable 0x0800 /* enable hash filter */
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# define RxAddrFilterEnable 0x1000 /* enable address filter */
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#define RXMAX 0x640 /* Max receive packet size */
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#define RXMIN 0x650 /* Min receive packet size */
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#define MADD2 0x660 /* our enet address, high part */
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#define MADD1 0x670 /* our enet address, middle part */
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#define MADD0 0x680 /* our enet address, low part */
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#define FRCNT 0x690 /* receive frame counter */
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#define LECNT 0x6a0 /* Receive excess length error counter */
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#define AECNT 0x6b0 /* Receive misaligned error counter */
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#define FECNT 0x6c0 /* Receive CRC error counter */
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#define RXSM 0x6d0 /* Receive state machine */
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#define RXCV 0x6e0 /* Receive code violation */
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#define BHASH3 0x700 /* multicast hash register */
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#define BHASH2 0x710 /* multicast hash register */
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#define BHASH1 0x720 /* multicast hash register */
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#define BHASH0 0x730 /* multicast hash register */
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#define AFR2 0x740 /* address filtering setup? */
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#define AFR1 0x750 /* address filtering setup? */
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#define AFR0 0x760 /* address filtering setup? */
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#define AFCR 0x770 /* address filter compare register? */
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# define EnableAllCompares 0x0fff
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/* bits in XIFC */
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