/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors: Dave Airlie <airlied@redhat.com>
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*/
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#ifndef __AST_DRV_H__
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#define __AST_DRV_H__
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_mode.h>
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#include <drm/drm_framebuffer.h>
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#include <drm/drm_fb_helper.h>
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#define DRIVER_AUTHOR "Dave Airlie"
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#define DRIVER_NAME "ast"
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#define DRIVER_DESC "AST"
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#define DRIVER_DATE "20120228"
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#define DRIVER_MAJOR 0
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#define DRIVER_MINOR 1
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#define DRIVER_PATCHLEVEL 0
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#define PCI_CHIP_AST2000 0x2000
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#define PCI_CHIP_AST2100 0x2010
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enum ast_chip {
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AST2000,
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AST2100,
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AST1100,
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AST2200,
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AST2150,
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AST2300,
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AST2400,
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AST2500,
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};
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enum ast_tx_chip {
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AST_TX_NONE,
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AST_TX_SIL164,
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AST_TX_ITE66121,
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AST_TX_DP501,
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};
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#define AST_DRAM_512Mx16 0
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#define AST_DRAM_1Gx16 1
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#define AST_DRAM_512Mx32 2
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#define AST_DRAM_1Gx32 3
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#define AST_DRAM_2Gx16 6
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#define AST_DRAM_4Gx16 7
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#define AST_DRAM_8Gx16 8
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#define AST_MAX_HWC_WIDTH 64
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#define AST_MAX_HWC_HEIGHT 64
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#define AST_HWC_SIZE (AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
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#define AST_HWC_SIGNATURE_SIZE 32
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#define AST_DEFAULT_HWC_NUM 2
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/* define for signature structure */
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#define AST_HWC_SIGNATURE_CHECKSUM 0x00
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#define AST_HWC_SIGNATURE_SizeX 0x04
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#define AST_HWC_SIGNATURE_SizeY 0x08
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#define AST_HWC_SIGNATURE_X 0x0C
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#define AST_HWC_SIGNATURE_Y 0x10
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#define AST_HWC_SIGNATURE_HOTSPOTX 0x14
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#define AST_HWC_SIGNATURE_HOTSPOTY 0x18
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struct ast_i2c_chan {
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struct i2c_adapter adapter;
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struct drm_device *dev;
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struct i2c_algo_bit_data bit;
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};
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struct ast_connector {
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struct drm_connector base;
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struct ast_i2c_chan *i2c;
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};
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static inline struct ast_connector *
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to_ast_connector(struct drm_connector *connector)
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{
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return container_of(connector, struct ast_connector, base);
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}
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struct ast_private {
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struct drm_device base;
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void __iomem *regs;
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void __iomem *ioregs;
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void __iomem *dp501_fw_buf;
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enum ast_chip chip;
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bool vga2_clone;
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uint32_t dram_bus_width;
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uint32_t dram_type;
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uint32_t mclk;
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int fb_mtrr;
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struct {
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struct drm_gem_vram_object *gbo[AST_DEFAULT_HWC_NUM];
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void __iomem *vaddr[AST_DEFAULT_HWC_NUM];
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unsigned int next_index;
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} cursor;
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struct drm_plane primary_plane;
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struct drm_plane cursor_plane;
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struct drm_crtc crtc;
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struct drm_encoder encoder;
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struct ast_connector connector;
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bool support_wide_screen;
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enum {
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ast_use_p2a,
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ast_use_dt,
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ast_use_defaults
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} config_mode;
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enum ast_tx_chip tx_chip_type;
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u8 dp501_maxclk;
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u8 *dp501_fw_addr;
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const struct firmware *dp501_fw; /* dp501 fw */
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};
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static inline struct ast_private *to_ast_private(struct drm_device *dev)
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{
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return container_of(dev, struct ast_private, base);
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}
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struct ast_private *ast_device_create(struct drm_driver *drv,
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struct pci_dev *pdev,
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unsigned long flags);
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#define AST_IO_AR_PORT_WRITE (0x40)
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#define AST_IO_MISC_PORT_WRITE (0x42)
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#define AST_IO_VGA_ENABLE_PORT (0x43)
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#define AST_IO_SEQ_PORT (0x44)
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#define AST_IO_DAC_INDEX_READ (0x47)
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#define AST_IO_DAC_INDEX_WRITE (0x48)
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#define AST_IO_DAC_DATA (0x49)
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#define AST_IO_GR_PORT (0x4E)
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#define AST_IO_CRTC_PORT (0x54)
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#define AST_IO_INPUT_STATUS1_READ (0x5A)
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#define AST_IO_MISC_PORT_READ (0x4C)
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#define AST_IO_MM_OFFSET (0x380)
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#define AST_IO_VGAIR1_VREFRESH BIT(3)
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#define __ast_read(x) \
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static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
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u##x val = 0;\
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val = ioread##x(ast->regs + reg); \
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return val;\
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}
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__ast_read(8);
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__ast_read(16);
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__ast_read(32)
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#define __ast_io_read(x) \
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static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
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u##x val = 0;\
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val = ioread##x(ast->ioregs + reg); \
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return val;\
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}
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__ast_io_read(8);
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__ast_io_read(16);
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__ast_io_read(32);
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#define __ast_write(x) \
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static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
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iowrite##x(val, ast->regs + reg);\
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}
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__ast_write(8);
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__ast_write(16);
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__ast_write(32);
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#define __ast_io_write(x) \
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static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
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iowrite##x(val, ast->ioregs + reg);\
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}
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__ast_io_write(8);
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__ast_io_write(16);
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#undef __ast_io_write
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static inline void ast_set_index_reg(struct ast_private *ast,
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uint32_t base, uint8_t index,
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uint8_t val)
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{
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ast_io_write16(ast, base, ((u16)val << 8) | index);
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}
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void ast_set_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index,
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uint8_t mask, uint8_t val);
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uint8_t ast_get_index_reg(struct ast_private *ast,
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uint32_t base, uint8_t index);
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uint8_t ast_get_index_reg_mask(struct ast_private *ast,
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uint32_t base, uint8_t index, uint8_t mask);
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static inline void ast_open_key(struct ast_private *ast)
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{
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
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}
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#define AST_VIDMEM_SIZE_8M 0x00800000
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#define AST_VIDMEM_SIZE_16M 0x01000000
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#define AST_VIDMEM_SIZE_32M 0x02000000
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#define AST_VIDMEM_SIZE_64M 0x04000000
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#define AST_VIDMEM_SIZE_128M 0x08000000
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#define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
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struct ast_vbios_stdtable {
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u8 misc;
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u8 seq[4];
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u8 crtc[25];
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u8 ar[20];
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u8 gr[9];
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};
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struct ast_vbios_enhtable {
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u32 ht;
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u32 hde;
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u32 hfp;
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u32 hsync;
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u32 vt;
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u32 vde;
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u32 vfp;
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u32 vsync;
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u32 dclk_index;
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u32 flags;
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u32 refresh_rate;
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u32 refresh_rate_index;
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u32 mode_id;
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};
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struct ast_vbios_dclk_info {
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u8 param1;
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u8 param2;
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u8 param3;
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};
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struct ast_vbios_mode_info {
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const struct ast_vbios_stdtable *std_table;
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const struct ast_vbios_enhtable *enh_table;
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};
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struct ast_crtc_state {
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struct drm_crtc_state base;
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/* Last known format of primary plane */
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const struct drm_format_info *format;
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struct ast_vbios_mode_info vbios_mode_info;
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};
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#define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
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int ast_mode_config_init(struct ast_private *ast);
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#define AST_MM_ALIGN_SHIFT 4
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#define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
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#define AST_DP501_FW_VERSION_MASK GENMASK(7, 4)
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#define AST_DP501_FW_VERSION_1 BIT(4)
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#define AST_DP501_PNP_CONNECTED BIT(1)
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#define AST_DP501_DEFAULT_DCLK 65
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#define AST_DP501_GBL_VERSION 0xf000
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#define AST_DP501_PNPMONITOR 0xf010
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#define AST_DP501_LINKRATE 0xf014
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#define AST_DP501_EDID_DATA 0xf020
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int ast_mm_init(struct ast_private *ast);
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/* ast post */
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void ast_enable_vga(struct drm_device *dev);
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void ast_enable_mmio(struct drm_device *dev);
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bool ast_is_vga_enabled(struct drm_device *dev);
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void ast_post_gpu(struct drm_device *dev);
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u32 ast_mindwm(struct ast_private *ast, u32 r);
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void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
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/* ast dp501 */
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void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
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bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
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bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
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u8 ast_get_dp501_max_clk(struct drm_device *dev);
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void ast_init_3rdtx(struct drm_device *dev);
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/* ast_cursor.c */
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int ast_cursor_init(struct ast_private *ast);
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int ast_cursor_blit(struct ast_private *ast, struct drm_framebuffer *fb);
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void ast_cursor_page_flip(struct ast_private *ast);
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void ast_cursor_show(struct ast_private *ast, int x, int y,
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unsigned int offset_x, unsigned int offset_y);
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void ast_cursor_hide(struct ast_private *ast);
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#endif
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