/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PAGE_64_DEFS_H
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#define _ASM_X86_PAGE_64_DEFS_H
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#ifndef __ASSEMBLY__
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#include <asm/kaslr.h>
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#endif
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#ifdef CONFIG_KASAN
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#define KASAN_STACK_ORDER 1
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#else
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#define KASAN_STACK_ORDER 0
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#endif
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#define THREAD_SIZE_ORDER (2 + KASAN_STACK_ORDER)
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#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
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#define EXCEPTION_STACK_ORDER (1 + KASAN_STACK_ORDER)
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#define EXCEPTION_STKSZ (PAGE_SIZE << EXCEPTION_STACK_ORDER)
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#define IRQ_STACK_ORDER (2 + KASAN_STACK_ORDER)
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#define IRQ_STACK_SIZE (PAGE_SIZE << IRQ_STACK_ORDER)
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/*
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* The index for the tss.ist[] array. The hardware limit is 7 entries.
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*/
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#define IST_INDEX_DF 0
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#define IST_INDEX_NMI 1
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#define IST_INDEX_DB 2
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#define IST_INDEX_MCE 3
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#define IST_INDEX_VC 4
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/*
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* Set __PAGE_OFFSET to the most negative possible address +
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* PGDIR_SIZE*17 (pgd slot 273).
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*
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* The gap is to allow a space for LDT remap for PTI (1 pgd slot) and space for
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* a hypervisor (16 slots). Choosing 16 slots for a hypervisor is arbitrary,
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* but it's what Xen requires.
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*/
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#define __PAGE_OFFSET_BASE_L5 _AC(0xff11000000000000, UL)
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#define __PAGE_OFFSET_BASE_L4 _AC(0xffff888000000000, UL)
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#ifdef CONFIG_DYNAMIC_MEMORY_LAYOUT
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#define __PAGE_OFFSET page_offset_base
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#else
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#define __PAGE_OFFSET __PAGE_OFFSET_BASE_L4
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#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
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#define __START_KERNEL_map _AC(0xffffffff80000000, UL)
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/* See Documentation/x86/x86_64/mm.rst for a description of the memory map. */
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#define __PHYSICAL_MASK_SHIFT 52
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#ifdef CONFIG_X86_5LEVEL
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#define __VIRTUAL_MASK_SHIFT (pgtable_l5_enabled() ? 56 : 47)
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#else
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#define __VIRTUAL_MASK_SHIFT 47
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#endif
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/*
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* User space process size. This is the first address outside the user range.
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* There are a few constraints that determine this:
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*
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* On Intel CPUs, if a SYSCALL instruction is at the highest canonical
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* address, then that syscall will enter the kernel with a
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* non-canonical return address, and SYSRET will explode dangerously.
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* We avoid this particular problem by preventing anything executable
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* from being mapped at the maximum canonical address.
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*
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* On AMD CPUs in the Ryzen family, there's a nasty bug in which the
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* CPUs malfunction if they execute code from the highest canonical page.
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* They'll speculate right off the end of the canonical space, and
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* bad things happen. This is worked around in the same way as the
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* Intel problem.
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*
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* With page table isolation enabled, we map the LDT in ... [stay tuned]
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*/
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#define TASK_SIZE_MAX ((_AC(1,UL) << __VIRTUAL_MASK_SHIFT) - PAGE_SIZE)
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#define DEFAULT_MAP_WINDOW ((1UL << 47) - PAGE_SIZE)
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
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0xc0000000 : 0xFFFFe000)
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#define TASK_SIZE_LOW (test_thread_flag(TIF_ADDR32) ? \
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IA32_PAGE_OFFSET : DEFAULT_MAP_WINDOW)
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#define TASK_SIZE (test_thread_flag(TIF_ADDR32) ? \
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IA32_PAGE_OFFSET : TASK_SIZE_MAX)
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#define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
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IA32_PAGE_OFFSET : TASK_SIZE_MAX)
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#define STACK_TOP TASK_SIZE_LOW
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#define STACK_TOP_MAX TASK_SIZE_MAX
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/*
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* Maximum kernel image size is limited to 1 GiB, due to the fixmap living
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* in the next 1 GiB (see level2_kernel_pgt in arch/x86/kernel/head_64.S).
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*
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* On KASLR use 1 GiB by default, leaving 1 GiB for modules once the
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* page tables are fully set up.
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*
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* If KASLR is disabled we can shrink it to 0.5 GiB and increase the size
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* of the modules area to 1.5 GiB.
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*/
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#ifdef CONFIG_RANDOMIZE_BASE
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#define KERNEL_IMAGE_SIZE (1024 * 1024 * 1024)
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#else
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#define KERNEL_IMAGE_SIZE (512 * 1024 * 1024)
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#endif
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#endif /* _ASM_X86_PAGE_64_DEFS_H */
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