// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-omap2/id.c
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*
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* OMAP2 CPU identification code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Written by Tony Lindgren <tony@atomide.com>
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*
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* Copyright (C) 2009-11 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#ifdef CONFIG_SOC_BUS
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#include <linux/sys_soc.h>
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#endif
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#include <asm/cputype.h>
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#include "common.h"
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#include "id.h"
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#include "soc.h"
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#include "control.h"
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#define OMAP4_SILICON_TYPE_STANDARD 0x01
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#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
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#define OMAP_SOC_MAX_NAME_LENGTH 16
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static unsigned int omap_revision;
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static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
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static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
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u32 omap_features;
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unsigned int omap_rev(void)
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{
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return omap_revision;
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}
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EXPORT_SYMBOL(omap_rev);
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int omap_type(void)
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{
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static u32 val = OMAP2_DEVICETYPE_MASK;
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if (val < OMAP2_DEVICETYPE_MASK)
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return val;
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if (soc_is_omap24xx()) {
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val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
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} else if (soc_is_ti81xx()) {
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val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
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} else if (soc_is_am33xx() || soc_is_am43xx()) {
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val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
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} else if (soc_is_omap34xx()) {
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val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
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} else if (soc_is_omap44xx()) {
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val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
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} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
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val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
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val &= OMAP5_DEVICETYPE_MASK;
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val >>= 6;
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goto out;
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} else {
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pr_err("Cannot detect omap type!\n");
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goto out;
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}
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val &= OMAP2_DEVICETYPE_MASK;
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val >>= 8;
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out:
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return val;
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}
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EXPORT_SYMBOL(omap_type);
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/*----------------------------------------------------------------------------*/
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#define OMAP_TAP_IDCODE 0x0204
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#define OMAP_TAP_DIE_ID_0 0x0218
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#define OMAP_TAP_DIE_ID_1 0x021C
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#define OMAP_TAP_DIE_ID_2 0x0220
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#define OMAP_TAP_DIE_ID_3 0x0224
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#define OMAP_TAP_DIE_ID_44XX_0 0x0200
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#define OMAP_TAP_DIE_ID_44XX_1 0x0208
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#define OMAP_TAP_DIE_ID_44XX_2 0x020c
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#define OMAP_TAP_DIE_ID_44XX_3 0x0210
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#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
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struct omap_id {
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u16 hawkeye; /* Silicon type (Hawkeye id) */
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u8 dev; /* Device type from production_id reg */
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u32 type; /* Combined type id copied to omap_revision */
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};
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/* Register values to detect the OMAP version */
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static struct omap_id omap_ids[] __initdata = {
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{ .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
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{ .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
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{ .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
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{ .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
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{ .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
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{ .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
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};
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static void __iomem *tap_base;
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static u16 tap_prod_id;
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void omap_get_die_id(struct omap_die_id *odi)
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{
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if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
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odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
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odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
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odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
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odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
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return;
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}
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odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
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odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
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odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
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odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
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}
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static int __init omap_feed_randpool(void)
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{
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struct omap_die_id odi;
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/* Throw the die ID into the entropy pool at boot */
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omap_get_die_id(&odi);
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add_device_randomness(&odi, sizeof(odi));
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return 0;
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}
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omap_device_initcall(omap_feed_randpool);
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void __init omap2xxx_check_revision(void)
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{
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int i, j;
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u32 idcode, prod_id;
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u16 hawkeye;
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u8 dev_type, rev;
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struct omap_die_id odi;
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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prod_id = read_tap_reg(tap_prod_id);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0x0f;
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dev_type = (prod_id >> 16) & 0x0f;
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omap_get_die_id(&odi);
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pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
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idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
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pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
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pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
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odi.id_1, (odi.id_1 >> 28) & 0xf);
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pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
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pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
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pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
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prod_id, dev_type);
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/* Check hawkeye ids */
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for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
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if (hawkeye == omap_ids[i].hawkeye)
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break;
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}
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if (i == ARRAY_SIZE(omap_ids)) {
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printk(KERN_ERR "Unknown OMAP CPU id\n");
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return;
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}
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for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
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if (dev_type == omap_ids[j].dev)
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break;
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}
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if (j == ARRAY_SIZE(omap_ids)) {
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pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
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omap_ids[i].type >> 16);
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j = i;
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}
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sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
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sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
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pr_info("%s", soc_name);
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if ((omap_rev() >> 8) & 0x0f)
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pr_cont("%s", soc_rev);
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pr_cont("\n");
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}
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#define OMAP3_SHOW_FEATURE(feat) \
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if (omap3_has_ ##feat()) \
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n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
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static void __init omap3_cpuinfo(void)
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{
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const char *cpu_name;
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char buf[64];
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int n = 0;
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memset(buf, 0, sizeof(buf));
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/*
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* OMAP3430 and OMAP3530 are assumed to be same.
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*
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* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
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* on available features. Upon detection, update the CPU id
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* and CPU class bits.
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*/
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if (soc_is_omap3630()) {
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if (omap3_has_iva() && omap3_has_sgx()) {
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cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
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} else if (omap3_has_iva()) {
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cpu_name = "DM3725";
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} else if (omap3_has_sgx()) {
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cpu_name = "OMAP3615/AM3715";
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} else {
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cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
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}
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} else if (soc_is_am35xx()) {
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cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
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} else if (soc_is_ti816x()) {
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cpu_name = "TI816X";
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} else if (soc_is_am335x()) {
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cpu_name = "AM335X";
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} else if (soc_is_am437x()) {
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cpu_name = "AM437x";
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} else if (soc_is_ti814x()) {
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cpu_name = "TI814X";
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} else if (omap3_has_iva() && omap3_has_sgx()) {
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/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
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cpu_name = "OMAP3430/3530";
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} else if (omap3_has_iva()) {
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cpu_name = "OMAP3525";
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} else if (omap3_has_sgx()) {
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cpu_name = "OMAP3515";
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} else {
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cpu_name = "OMAP3503";
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}
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scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
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/* Print verbose information */
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n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
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OMAP3_SHOW_FEATURE(l2cache);
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OMAP3_SHOW_FEATURE(iva);
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OMAP3_SHOW_FEATURE(sgx);
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OMAP3_SHOW_FEATURE(neon);
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OMAP3_SHOW_FEATURE(isp);
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OMAP3_SHOW_FEATURE(192mhz_clk);
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if (*(buf + n - 1) == ' ')
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n--;
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n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
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pr_info("%s", buf);
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}
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#define OMAP3_CHECK_FEATURE(status,feat) \
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if (((status & OMAP3_ ##feat## _MASK) \
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>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
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omap_features |= OMAP3_HAS_ ##feat; \
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}
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void __init omap3xxx_check_features(void)
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{
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u32 status;
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omap_features = 0;
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status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
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OMAP3_CHECK_FEATURE(status, L2CACHE);
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OMAP3_CHECK_FEATURE(status, IVA);
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OMAP3_CHECK_FEATURE(status, SGX);
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OMAP3_CHECK_FEATURE(status, NEON);
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OMAP3_CHECK_FEATURE(status, ISP);
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if (soc_is_omap3630())
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omap_features |= OMAP3_HAS_192MHZ_CLK;
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if (soc_is_omap3430() || soc_is_omap3630())
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omap_features |= OMAP3_HAS_IO_WAKEUP;
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if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
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omap_rev() == OMAP3430_REV_ES3_1_2)
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omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
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omap_features |= OMAP3_HAS_SDRC;
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/*
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* am35x fixups:
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* - The am35x Chip ID register has bits 12, 7:5, and 3:2 marked as
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* reserved and therefore return 0 when read. Unfortunately,
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* OMAP3_CHECK_FEATURE() will interpret some of those zeroes to
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* mean that a feature is present even though it isn't so clear
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* the incorrectly set feature bits.
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*/
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if (soc_is_am35xx())
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omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
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/*
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* TODO: Get additional info (where applicable)
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* e.g. Size of L2 cache.
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*/
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omap3_cpuinfo();
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}
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void __init omap4xxx_check_features(void)
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{
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u32 si_type;
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si_type =
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(read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
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if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
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omap_features = OMAP4_HAS_PERF_SILICON;
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}
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void __init ti81xx_check_features(void)
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{
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omap_features = OMAP3_HAS_NEON;
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omap3_cpuinfo();
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}
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void __init am33xx_check_features(void)
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{
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u32 status;
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omap_features = OMAP3_HAS_NEON;
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status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
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if (status & AM33XX_SGX_MASK)
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omap_features |= OMAP3_HAS_SGX;
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omap3_cpuinfo();
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}
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void __init omap3xxx_check_revision(void)
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{
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const char *cpu_rev;
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u32 cpuid, idcode;
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u16 hawkeye;
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u8 rev;
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/*
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* We cannot access revision registers on ES1.0.
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* If the processor type is Cortex-A8 and the revision is 0x0
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* it means its Cortex r0p0 which is 3430 ES1.0.
|
*/
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cpuid = read_cpuid_id();
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if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
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omap_revision = OMAP3430_REV_ES1_0;
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cpu_rev = "1.0";
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return;
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}
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/*
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* Detection for 34xx ES2.0 and above can be done with just
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* hawkeye and rev. See TRM 1.5.2 Device Identification.
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* Note that rev does not map directly to our defined processor
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* revision numbers as ES1.0 uses value 0.
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*/
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idcode = read_tap_reg(OMAP_TAP_IDCODE);
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hawkeye = (idcode >> 12) & 0xffff;
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rev = (idcode >> 28) & 0xff;
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switch (hawkeye) {
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case 0xb7ae:
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/* Handle 34xx/35xx devices */
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switch (rev) {
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case 0: /* Take care of early samples */
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case 1:
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omap_revision = OMAP3430_REV_ES2_0;
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cpu_rev = "2.0";
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break;
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case 2:
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omap_revision = OMAP3430_REV_ES2_1;
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cpu_rev = "2.1";
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break;
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case 3:
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omap_revision = OMAP3430_REV_ES3_0;
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cpu_rev = "3.0";
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break;
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case 4:
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omap_revision = OMAP3430_REV_ES3_1;
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cpu_rev = "3.1";
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break;
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case 7:
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default:
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/* Use the latest known revision as default */
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omap_revision = OMAP3430_REV_ES3_1_2;
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cpu_rev = "3.1.2";
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}
|
break;
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case 0xb868:
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/*
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* Handle OMAP/AM 3505/3517 devices
|
*
|
* Set the device to be OMAP3517 here. Actual device
|
* is identified later based on the features.
|
*/
|
switch (rev) {
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case 0:
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omap_revision = AM35XX_REV_ES1_0;
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cpu_rev = "1.0";
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break;
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case 1:
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default:
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omap_revision = AM35XX_REV_ES1_1;
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cpu_rev = "1.1";
|
}
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break;
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case 0xb891:
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/* Handle 36xx devices */
|
|
switch(rev) {
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case 0: /* Take care of early samples */
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omap_revision = OMAP3630_REV_ES1_0;
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cpu_rev = "1.0";
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break;
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case 1:
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omap_revision = OMAP3630_REV_ES1_1;
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cpu_rev = "1.1";
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break;
|
case 2:
|
default:
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omap_revision = OMAP3630_REV_ES1_2;
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cpu_rev = "1.2";
|
}
|
break;
|
case 0xb81e:
|
switch (rev) {
|
case 0:
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omap_revision = TI8168_REV_ES1_0;
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cpu_rev = "1.0";
|
break;
|
case 1:
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omap_revision = TI8168_REV_ES1_1;
|
cpu_rev = "1.1";
|
break;
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case 2:
|
omap_revision = TI8168_REV_ES2_0;
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cpu_rev = "2.0";
|
break;
|
case 3:
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default:
|
omap_revision = TI8168_REV_ES2_1;
|
cpu_rev = "2.1";
|
}
|
break;
|
case 0xb944:
|
switch (rev) {
|
case 0:
|
omap_revision = AM335X_REV_ES1_0;
|
cpu_rev = "1.0";
|
break;
|
case 1:
|
omap_revision = AM335X_REV_ES2_0;
|
cpu_rev = "2.0";
|
break;
|
case 2:
|
default:
|
omap_revision = AM335X_REV_ES2_1;
|
cpu_rev = "2.1";
|
break;
|
}
|
break;
|
case 0xb98c:
|
switch (rev) {
|
case 0:
|
omap_revision = AM437X_REV_ES1_0;
|
cpu_rev = "1.0";
|
break;
|
case 1:
|
omap_revision = AM437X_REV_ES1_1;
|
cpu_rev = "1.1";
|
break;
|
case 2:
|
default:
|
omap_revision = AM437X_REV_ES1_2;
|
cpu_rev = "1.2";
|
break;
|
}
|
break;
|
case 0xb8f2:
|
case 0xb968:
|
switch (rev) {
|
case 0:
|
case 1:
|
omap_revision = TI8148_REV_ES1_0;
|
cpu_rev = "1.0";
|
break;
|
case 2:
|
omap_revision = TI8148_REV_ES2_0;
|
cpu_rev = "2.0";
|
break;
|
case 3:
|
default:
|
omap_revision = TI8148_REV_ES2_1;
|
cpu_rev = "2.1";
|
break;
|
}
|
break;
|
default:
|
/* Unknown default to latest silicon rev as default */
|
omap_revision = OMAP3630_REV_ES1_2;
|
cpu_rev = "1.2";
|
pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
|
hawkeye);
|
}
|
sprintf(soc_rev, "ES%s", cpu_rev);
|
}
|
|
void __init omap4xxx_check_revision(void)
|
{
|
u32 idcode;
|
u16 hawkeye;
|
u8 rev;
|
|
/*
|
* The IC rev detection is done with hawkeye and rev.
|
* Note that rev does not map directly to defined processor
|
* revision numbers as ES1.0 uses value 0.
|
*/
|
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
hawkeye = (idcode >> 12) & 0xffff;
|
rev = (idcode >> 28) & 0xf;
|
|
/*
|
* Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
|
* Use ARM register to detect the correct ES version
|
*/
|
if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
|
idcode = read_cpuid_id();
|
rev = (idcode & 0xf) - 1;
|
}
|
|
switch (hawkeye) {
|
case 0xb852:
|
switch (rev) {
|
case 0:
|
omap_revision = OMAP4430_REV_ES1_0;
|
break;
|
case 1:
|
default:
|
omap_revision = OMAP4430_REV_ES2_0;
|
}
|
break;
|
case 0xb95c:
|
switch (rev) {
|
case 3:
|
omap_revision = OMAP4430_REV_ES2_1;
|
break;
|
case 4:
|
omap_revision = OMAP4430_REV_ES2_2;
|
break;
|
case 6:
|
default:
|
omap_revision = OMAP4430_REV_ES2_3;
|
}
|
break;
|
case 0xb94e:
|
switch (rev) {
|
case 0:
|
omap_revision = OMAP4460_REV_ES1_0;
|
break;
|
case 2:
|
default:
|
omap_revision = OMAP4460_REV_ES1_1;
|
break;
|
}
|
break;
|
case 0xb975:
|
switch (rev) {
|
case 0:
|
default:
|
omap_revision = OMAP4470_REV_ES1_0;
|
break;
|
}
|
break;
|
default:
|
/* Unknown default to latest silicon rev as default */
|
omap_revision = OMAP4430_REV_ES2_3;
|
}
|
|
sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
|
sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
|
(omap_rev() >> 8) & 0xf);
|
pr_info("%s %s\n", soc_name, soc_rev);
|
}
|
|
void __init omap5xxx_check_revision(void)
|
{
|
u32 idcode;
|
u16 hawkeye;
|
u8 rev;
|
|
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
hawkeye = (idcode >> 12) & 0xffff;
|
rev = (idcode >> 28) & 0xff;
|
switch (hawkeye) {
|
case 0xb942:
|
switch (rev) {
|
case 0:
|
/* No support for ES1.0 Test chip */
|
BUG();
|
case 1:
|
default:
|
omap_revision = OMAP5430_REV_ES2_0;
|
}
|
break;
|
|
case 0xb998:
|
switch (rev) {
|
case 0:
|
/* No support for ES1.0 Test chip */
|
BUG();
|
case 1:
|
default:
|
omap_revision = OMAP5432_REV_ES2_0;
|
}
|
break;
|
|
default:
|
/* Unknown default to latest silicon rev as default*/
|
omap_revision = OMAP5430_REV_ES2_0;
|
}
|
|
sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
|
sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
|
|
pr_info("%s %s\n", soc_name, soc_rev);
|
}
|
|
void __init dra7xxx_check_revision(void)
|
{
|
u32 idcode;
|
u16 hawkeye;
|
u8 rev, package;
|
struct omap_die_id odi;
|
|
omap_get_die_id(&odi);
|
package = (odi.id_2 >> 16) & 0x3;
|
idcode = read_tap_reg(OMAP_TAP_IDCODE);
|
hawkeye = (idcode >> 12) & 0xffff;
|
rev = (idcode >> 28) & 0xff;
|
switch (hawkeye) {
|
case 0xbb50:
|
switch (rev) {
|
case 0:
|
default:
|
switch (package) {
|
case 0x2:
|
omap_revision = DRA762_ABZ_REV_ES1_0;
|
break;
|
case 0x3:
|
omap_revision = DRA762_ACD_REV_ES1_0;
|
break;
|
default:
|
omap_revision = DRA762_REV_ES1_0;
|
break;
|
}
|
break;
|
}
|
break;
|
|
case 0xb990:
|
switch (rev) {
|
case 0:
|
omap_revision = DRA752_REV_ES1_0;
|
break;
|
case 1:
|
omap_revision = DRA752_REV_ES1_1;
|
break;
|
case 2:
|
default:
|
omap_revision = DRA752_REV_ES2_0;
|
break;
|
}
|
break;
|
|
case 0xb9bc:
|
switch (rev) {
|
case 0:
|
omap_revision = DRA722_REV_ES1_0;
|
break;
|
case 1:
|
omap_revision = DRA722_REV_ES2_0;
|
break;
|
case 2:
|
default:
|
omap_revision = DRA722_REV_ES2_1;
|
break;
|
}
|
break;
|
|
default:
|
/* Unknown default to latest silicon rev as default*/
|
pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
|
__func__, idcode, hawkeye, rev);
|
omap_revision = DRA752_REV_ES2_0;
|
}
|
|
sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
|
sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
|
(omap_rev() >> 8) & 0xf);
|
|
pr_info("%s %s\n", soc_name, soc_rev);
|
}
|
|
/*
|
* Set up things for map_io and processor detection later on. Gets called
|
* pretty much first thing from board init. For multi-omap, this gets
|
* cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
|
* detect the exact revision later on in omap2_detect_revision() once map_io
|
* is done.
|
*/
|
void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
|
{
|
omap_revision = class;
|
tap_base = tap;
|
|
/* XXX What is this intended to do? */
|
if (soc_is_omap34xx())
|
tap_prod_id = 0x0210;
|
else
|
tap_prod_id = 0x0208;
|
}
|
|
#ifdef CONFIG_SOC_BUS
|
|
static const char * const omap_types[] = {
|
[OMAP2_DEVICE_TYPE_TEST] = "TST",
|
[OMAP2_DEVICE_TYPE_EMU] = "EMU",
|
[OMAP2_DEVICE_TYPE_SEC] = "HS",
|
[OMAP2_DEVICE_TYPE_GP] = "GP",
|
[OMAP2_DEVICE_TYPE_BAD] = "BAD",
|
};
|
|
static const char * __init omap_get_family(void)
|
{
|
if (soc_is_omap24xx())
|
return kasprintf(GFP_KERNEL, "OMAP2");
|
else if (soc_is_omap34xx())
|
return kasprintf(GFP_KERNEL, "OMAP3");
|
else if (soc_is_omap44xx())
|
return kasprintf(GFP_KERNEL, "OMAP4");
|
else if (soc_is_omap54xx())
|
return kasprintf(GFP_KERNEL, "OMAP5");
|
else if (soc_is_am33xx() || soc_is_am335x())
|
return kasprintf(GFP_KERNEL, "AM33xx");
|
else if (soc_is_am43xx())
|
return kasprintf(GFP_KERNEL, "AM43xx");
|
else if (soc_is_dra7xx())
|
return kasprintf(GFP_KERNEL, "DRA7");
|
else
|
return kasprintf(GFP_KERNEL, "Unknown");
|
}
|
|
static ssize_t
|
type_show(struct device *dev, struct device_attribute *attr, char *buf)
|
{
|
return sprintf(buf, "%s\n", omap_types[omap_type()]);
|
}
|
|
static DEVICE_ATTR_RO(type);
|
|
static struct attribute *omap_soc_attrs[] = {
|
&dev_attr_type.attr,
|
NULL
|
};
|
|
ATTRIBUTE_GROUPS(omap_soc);
|
|
void __init omap_soc_device_init(void)
|
{
|
struct soc_device *soc_dev;
|
struct soc_device_attribute *soc_dev_attr;
|
|
soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
|
if (!soc_dev_attr)
|
return;
|
|
soc_dev_attr->machine = soc_name;
|
soc_dev_attr->family = omap_get_family();
|
soc_dev_attr->revision = soc_rev;
|
soc_dev_attr->custom_attr_group = omap_soc_groups[0];
|
|
soc_dev = soc_device_register(soc_dev_attr);
|
if (IS_ERR(soc_dev)) {
|
kfree(soc_dev_attr);
|
return;
|
}
|
}
|
#endif /* CONFIG_SOC_BUS */
|
