// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Joe.C <yingjoe.chen@mediatek.com>
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*
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*/
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#include <dt-bindings/clock/mt8135-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/mt8135-resets.h>
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#include "mt8135-pinfunc.h"
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "mediatek,mt8135";
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interrupt-parent = <&sysirq>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu2>;
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};
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core1 {
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cpu = <&cpu3>;
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};
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "mediatek,mt81xx-tz-smp";
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x001>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x100>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0x101>;
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};
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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trustzone-bootinfo@80002000 {
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compatible = "mediatek,trustzone-bootinfo";
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reg = <0 0x80002000 0 0x1000>;
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};
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};
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clocks {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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system_clk: dummy13m {
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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#clock-cells = <0>;
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};
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rtc_clk: dummy32k {
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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#clock-cells = <0>;
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};
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clk26m: clk26m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <13000000>;
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arm,cpu-registers-not-fw-configured;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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topckgen: topckgen@10000000 {
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compatible = "mediatek,mt8135-topckgen";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: infracfg@10001000 {
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#reset-cells = <1>;
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#clock-cells = <1>;
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compatible = "mediatek,mt8135-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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};
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pericfg: pericfg@10003000 {
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#reset-cells = <1>;
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#clock-cells = <1>;
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compatible = "mediatek,mt8135-pericfg", "syscon";
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reg = <0 0x10003000 0 0x1000>;
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};
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/*
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* Pinctrl access register at 0x10005000 and 0x1020c000 through
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* regmap. Register 0x1000b000 is used by EINT.
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*/
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt8135-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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};
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syscfg_pctl_a: syscfg_pctl_a@10005000 {
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compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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timer: timer@10008000 {
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compatible = "mediatek,mt8135-timer",
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"mediatek,mt6577-timer";
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reg = <0 0x10008000 0 0x80>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>, <&rtc_clk>;
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clock-names = "system-clk", "rtc-clk";
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};
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pwrap: pwrap@1000f000 {
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compatible = "mediatek,mt8135-pwrap";
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reg = <0 0x1000f000 0 0x1000>,
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<0 0x11017000 0 0x1000>;
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reg-names = "pwrap", "pwrap-bridge";
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
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<&pericfg MT8135_PERI_PWRAP_BRIDGE_SW_RST>;
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reset-names = "pwrap", "pwrap-bridge";
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clocks = <&clk26m>, <&clk26m>;
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clock-names = "spi", "wrap";
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};
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sysirq: interrupt-controller@10200030 {
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compatible = "mediatek,mt8135-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10200030 0 0x1c>;
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};
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apmixedsys: apmixedsys@10209000 {
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compatible = "mediatek,mt8135-apmixedsys";
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reg = <0 0x10209000 0 0x1000>;
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#clock-cells = <1>;
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};
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syscfg_pctl_b: syscfg_pctl_b@1020c000 {
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compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
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reg = <0 0x1020c000 0 0x1000>;
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};
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gic: interrupt-controller@10211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x10211000 0 0x1000>,
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<0 0x10212000 0 0x2000>,
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<0 0x10214000 0 0x2000>,
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<0 0x10216000 0 0x2000>;
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};
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uart0: serial@11006000 {
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compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
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reg = <0 0x11006000 0 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11007000 {
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compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
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reg = <0 0x11007000 0 0x400>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11008000 {
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compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
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reg = <0 0x11008000 0 0x400>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart3: serial@11009000 {
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compatible = "mediatek,mt8135-uart","mediatek,mt6577-uart";
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reg = <0 0x11009000 0 0x400>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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};
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};
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