// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
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*/
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/dts-v1/;
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#include "am33xx.dtsi"
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/ {
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model = "Newflow AM335x NanoBone";
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compatible = "ti,am33xx";
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cpus {
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cpu@0 {
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cpu0-supply = <&dcdc2_reg>;
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
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leds {
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compatible = "gpio-leds";
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led0 {
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label = "nanobone:green:usr1";
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gpios = <&gpio1 5 0>;
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default-state = "off";
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};
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};
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};
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&misc_pins>;
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misc_pins: misc_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */
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>;
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};
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gpmc_pins: gpmc_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */
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AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */
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AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */
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AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */
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>;
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};
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i2c0_pins: i2c0_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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uart0_pins: uart0_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
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>;
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};
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uart1_pins: uart1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7)
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7)
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AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
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>;
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};
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uart2_pins: uart2_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */
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AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */
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AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */
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>;
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};
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uart3_pins: uart3_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */
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AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
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>;
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};
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uart4_pins: uart4_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */
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AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */
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AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */
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>;
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};
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uart5_pins: uart5_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */
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AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */
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>;
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};
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mmc1_pins: mmc1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */
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AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
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AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */
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AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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rs485-rts-active-high;
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rs485-rx-during-tx;
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rs485-rts-delay = <1 1>;
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linux,rs485-enabled-at-boot-time;
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
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rs485-rts-active-high;
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rs485-rts-delay = <1 1>;
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linux,rs485-enabled-at-boot-time;
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart3_pins>;
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status = "okay";
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};
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&uart4 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart4_pins>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart5_pins>;
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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pinctrl-names = "default";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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gpio@20 {
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compatible = "microchip,mcp23017";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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tps: tps@24 {
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reg = <0x24>;
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};
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eeprom@53 {
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compatible = "microchip,24c02", "atmel,24c02";
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reg = <0x53>;
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pagesize = <8>;
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};
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rtc@68 {
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compatible = "dallas,ds1307";
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reg = <0x68>;
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};
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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status = "okay";
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gpmc,num-waitpins = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&gpmc_pins>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */
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<1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */
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nor@0,0 {
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reg = <0 0x00000000 0x08000000>;
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compatible = "cfi-flash";
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linux,mtd-name = "spansion,s29gl010p11t";
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bank-width = <2>;
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gpmc,mux-add-data = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <160>;
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gpmc,cs-wr-off-ns = <160>;
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gpmc,adv-on-ns = <10>;
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gpmc,adv-rd-off-ns = <30>;
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gpmc,adv-wr-off-ns = <30>;
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gpmc,oe-on-ns = <40>;
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gpmc,oe-off-ns = <160>;
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gpmc,we-on-ns = <40>;
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gpmc,we-off-ns = <160>;
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gpmc,rd-cycle-ns = <160>;
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gpmc,wr-cycle-ns = <160>;
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gpmc,access-ns = <150>;
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gpmc,page-burst-access-ns = <10>;
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gpmc,cycle2cycle-samecsen;
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gpmc,cycle2cycle-delay-ns = <20>;
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gpmc,wr-data-mux-bus-ns = <70>;
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gpmc,wr-access-ns = <80>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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MTD partition table
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===================
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+------------+-->0x00000000-> U-Boot start
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| |
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| |-->0x000BFFFF-> U-Boot end
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| |-->0x000C0000-> ENV1 start
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| |
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| |-->0x000DFFFF-> ENV1 end
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| |-->0x000E0000-> ENV2 start
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| |
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| |-->0x000FFFFF-> ENV2 end
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| |-->0x00100000-> Kernel start
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| |
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| |-->0x004FFFFF-> Kernel end
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| |-->0x00500000-> File system start
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| |
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| |-->0x01FFFFFF-> File system end
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| |-->0x02000000-> User data start
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| |
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| |-->0x03FFFFFF-> User data end
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| |-->0x04000000-> Data storage start
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| |
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+------------+-->0x08000000-> NOR end (Free end)
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*/
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partition@0 {
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label = "boot";
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reg = <0x00000000 0x000c0000>; /* 768KB */
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};
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partition@1 {
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label = "env1";
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reg = <0x000c0000 0x00020000>; /* 128KB */
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};
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partition@2 {
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label = "env2";
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reg = <0x000e0000 0x00020000>; /* 128KB */
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};
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partition@3 {
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label = "kernel";
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reg = <0x00100000 0x00400000>; /* 4MB */
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};
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partition@4 {
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label = "rootfs";
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reg = <0x00500000 0x01b00000>; /* 27MB */
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};
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partition@5 {
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label = "user";
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reg = <0x02000000 0x02000000>; /* 32MB */
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};
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partition@6 {
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label = "data";
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reg = <0x04000000 0x04000000>; /* 64MB */
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};
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};
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fram@1,0 {
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reg = <1 0x00000000 0x01000000>;
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bank-width = <2>;
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gpmc,mux-add-data = <2>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <160>;
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gpmc,cs-wr-off-ns = <160>;
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gpmc,adv-on-ns = <10>;
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gpmc,adv-rd-off-ns = <20>;
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gpmc,adv-wr-off-ns = <20>;
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gpmc,oe-on-ns = <30>;
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gpmc,oe-off-ns = <150>;
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gpmc,we-on-ns = <30>;
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gpmc,we-off-ns = <150>;
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gpmc,rd-cycle-ns = <160>;
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gpmc,wr-cycle-ns = <160>;
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gpmc,access-ns = <130>;
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gpmc,page-burst-access-ns = <10>;
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gpmc,cycle2cycle-samecsen;
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gpmc,cycle2cycle-diffcsen;
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gpmc,cycle2cycle-delay-ns = <10>;
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gpmc,wr-data-mux-bus-ns = <30>;
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gpmc,wr-access-ns = <0>;
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};
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};
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&mac {
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dual_emac;
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status = "okay";
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};
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&davinci_mdio {
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&cpsw_emac0 {
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phy-handle = <ðphy0>;
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phy-mode = "mii";
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dual_emac_res_vlan = <1>;
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};
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&cpsw_emac1 {
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phy-handle = <ðphy1>;
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phy-mode = "mii";
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dual_emac_res_vlan = <2>;
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};
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&mmc1 {
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status = "okay";
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vmmc-supply = <&ldo4_reg>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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bus-width = <4>;
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cd-gpios = <&gpio3 8 0>;
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wp-gpios = <&gpio3 18 0>;
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};
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#include "tps65217.dtsi"
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&tps {
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regulators {
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dcdc1_reg: regulator@0 {
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/* +1.5V voltage with ±4% tolerance */
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regulator-min-microvolt = <1450000>;
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regulator-max-microvolt = <1550000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc2_reg: regulator@1 {
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/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
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regulator-name = "vdd_mpu";
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regulator-min-microvolt = <915000>;
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regulator-max-microvolt = <1140000>;
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regulator-boot-on;
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regulator-always-on;
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};
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dcdc3_reg: regulator@2 {
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/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
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regulator-name = "vdd_core";
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regulator-min-microvolt = <915000>;
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regulator-max-microvolt = <1140000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: regulator@3 {
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/* +1.8V voltage with ±4% tolerance */
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <1870000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: regulator@4 {
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/* +3.3V voltage with ±4% tolerance */
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regulator-min-microvolt = <3175000>;
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regulator-max-microvolt = <3430000>;
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regulator-boot-on;
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regulator-always-on;
|
};
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ldo3_reg: regulator@5 {
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/* +1.8V voltage with ±4% tolerance */
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regulator-min-microvolt = <1750000>;
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regulator-max-microvolt = <1870000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: regulator@6 {
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/* +3.3V voltage with ±4% tolerance */
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regulator-min-microvolt = <3175000>;
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regulator-max-microvolt = <3430000>;
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regulator-boot-on;
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regulator-always-on;
|
};
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};
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};
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