/*
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* Copyright 2015 Annapurna Labs Ltd.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Alternatively, redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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/* SOC compatibility */
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compatible = "al,alpine";
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memory {
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device_type = "memory";
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reg = <0 0 0 0>;
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};
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/* CPU Configuration */
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "al,alpine-smp";
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cpu@0 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <1700000000>;
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};
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cpu@1 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <1>;
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clock-frequency = <1700000000>;
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};
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cpu@2 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <2>;
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clock-frequency = <1700000000>;
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};
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cpu@3 {
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compatible = "arm,cortex-a15";
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device_type = "cpu";
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reg = <3>;
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clock-frequency = <1700000000>;
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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ranges;
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arch-timer {
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compatible = "arm,cortex-a15-timer",
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"arm,armv7-timer";
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interrupts =
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<GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <50000000>;
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};
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/* Interrupt Controller */
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gic: interrupt-controller@fb001000 {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0xfb001000 0x0 0x1000>,
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<0x0 0xfb002000 0x0 0x2000>,
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<0x0 0xfb004000 0x0 0x2000>,
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<0x0 0xfb006000 0x0 0x2000>;
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interrupts =
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<GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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/* CPU Resume registers */
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cpu-resume@fbff5ec0 {
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compatible = "al,alpine-cpu-resume";
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reg = <0x0 0xfbff5ec0 0x0 0x30>;
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};
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/* North Bridge Service Registers */
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sysfabric-service@fb070000 {
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compatible = "al,alpine-sysfabric-service", "syscon";
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reg = <0x0 0xfb070000 0x0 0x10000>;
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};
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/* Performance Monitor Unit */
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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};
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uart0: uart@fd883000 {
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compatible = "ns16550a";
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reg = <0x0 0xfd883000 0x0 0x1000>;
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clock-frequency = <375000000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: uart@fd884000 {
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compatible = "ns16550a";
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reg = <0x0 0xfd884000 0x0 0x1000>;
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clock-frequency = <375000000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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/* Internal PCIe Controller */
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pcie@fbc00000 {
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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#interrupt-cells = <1>;
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reg = <0x0 0xfbc00000 0x0 0x100000>;
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interrupt-map-mask = <0xf800 0 0 7>;
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/* Add legacy interrupts for SATA devices only */
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interrupt-map = <0x4000 0 0 1 &gic 0 43 4>,
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<0x4800 0 0 1 &gic 0 44 4>;
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/* 32 bit non prefetchable memory space */
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ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
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bus-range = <0x00 0x00>;
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msi-parent = <&msix>;
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};
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msix: msix@fbe00000 {
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compatible = "al,alpine-msix";
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reg = <0x0 0xfbe00000 0x0 0x100000>;
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interrupt-controller;
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msi-controller;
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al,msi-base-spi = <96>;
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al,msi-num-spis = <64>;
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};
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};
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};
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