Device-Tree bindings for the NXP TDA1997x HDMI receiver
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The TDA19971/73 are HDMI video receivers.
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The TDA19971 Video port output pins can be used as follows:
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- RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
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- YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
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- YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
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- YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
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- YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
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- YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
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- YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
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- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
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The TDA19973 Video port output pins can be used as follows:
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- RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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- YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
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- YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
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- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
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The Video port output pins are mapped via 4-bit 'pin groups' allowing
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for a variety of connection possibilities including swapping pin order within
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pin groups. The video_portcfg device-tree property consists of register mapping
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pairs which map a chip-specific VP output register to a 4-bit pin group. If
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the pin group needs to be bit-swapped you can use the *_S pin-group defines.
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Required Properties:
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- compatible :
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- "nxp,tda19971" for the TDA19971
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- "nxp,tda19973" for the TDA19973
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- reg : I2C slave address
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- interrupts : The interrupt number
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- DOVDD-supply : Digital I/O supply
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- DVDD-supply : Digital Core supply
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- AVDD-supply : Analog supply
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- nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
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Optional Properties:
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- nxp,audout-format : DAI bus format: "i2s" or "spdif".
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- nxp,audout-width : width of audio output data bus (1-4).
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- nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
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- nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
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mclk.
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The port node shall contain one endpoint child node for its digital
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output video port, in accordance with the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Optional Endpoint Properties:
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The following three properties are defined in video-interfaces.txt and
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are valid for the output parallel bus endpoint:
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- hsync-active: Horizontal synchronization polarity. Defaults to active high.
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- vsync-active: Vertical synchronization polarity. Defaults to active high.
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- data-active: Data polarity. Defaults to active high.
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Examples:
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- VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
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16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
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hdmi-receiver@48 {
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compatible = "nxp,tda19971";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tda1997x>;
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reg = <0x48>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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DOVDD-supply = <®_3p3v>;
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AVDD-supply = <®_1p8v>;
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DVDD-supply = <®_1p8v>;
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/* audio */
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#sound-dai-cells = <0>;
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nxp,audout-format = "i2s";
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nxp,audout-layout = <0>;
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nxp,audout-width = <16>;
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nxp,audout-mclk-fs = <128>;
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/*
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* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
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* and Y[11:4] across 16bits in the same pixclk cycle.
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*/
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nxp,vidout-portcfg =
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/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
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< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
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/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
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< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
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/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
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< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
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/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
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< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
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port {
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tda1997x_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <16>;
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hsync-active = <1>;
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vsync-active = <1>;
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data-active = <1>;
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};
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};
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};
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- VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
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16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
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hdmi-receiver@48 {
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compatible = "nxp,tda19971";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tda1997x>;
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reg = <0x48>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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DOVDD-supply = <®_3p3v>;
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AVDD-supply = <®_1p8v>;
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DVDD-supply = <®_1p8v>;
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/* audio */
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#sound-dai-cells = <0>;
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nxp,audout-format = "i2s";
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nxp,audout-layout = <0>;
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nxp,audout-width = <16>;
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nxp,audout-mclk-fs = <128>;
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/*
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* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
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* and Y[11:4] across 16bits in the same pixclk cycle.
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*/
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nxp,vidout-portcfg =
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/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
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< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
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/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
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< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
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/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
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< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
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/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
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< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
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port {
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tda1997x_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <16>;
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hsync-active = <1>;
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vsync-active = <1>;
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data-active = <1>;
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};
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};
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};
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- VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
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16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
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hdmi-receiver@48 {
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compatible = "nxp,tda19971";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tda1997x>;
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reg = <0x48>;
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interrupt-parent = <&gpio1>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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DOVDD-supply = <®_3p3v>;
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AVDD-supply = <®_1p8v>;
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DVDD-supply = <®_1p8v>;
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/* audio */
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#sound-dai-cells = <0>;
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nxp,audout-format = "i2s";
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nxp,audout-layout = <0>;
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nxp,audout-width = <16>;
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nxp,audout-mclk-fs = <128>;
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/*
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* The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
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* 2 pixclk cycles.
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*/
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nxp,vidout-portcfg =
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/* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
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< TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
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/* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
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< TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
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port {
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tda1997x_to_ipu1_csi0_mux: endpoint {
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remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
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bus-width = <16>;
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hsync-active = <1>;
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vsync-active = <1>;
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data-active = <1>;
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};
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};
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};
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