* Analog Devices ADV748X video decoder with HDMI receiver
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The ADV7481 and ADV7482 are multi format video decoders with an integrated
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HDMI receiver. They can output CSI-2 on two independent outputs TXA and TXB
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from three input sources HDMI, analog and TTL.
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Required Properties:
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- compatible: Must contain one of the following
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- "adi,adv7481" for the ADV7481
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- "adi,adv7482" for the ADV7482
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- reg: I2C slave addresses
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The ADV748x has up to twelve 256-byte maps that can be accessed via the
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main I2C ports. Each map has it own I2C address and acts as a standard
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slave device on the I2C bus. The main address is mandatory, others are
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optional and remain at default values if not specified.
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Optional Properties:
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- interrupt-names: Should specify the interrupts as "intrq1", "intrq2" and/or
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"intrq3". All interrupts are optional. The "intrq3" interrupt
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is only available on the adv7481
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- interrupts: Specify the interrupt lines for the ADV748x
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- reg-names : Names of maps with programmable addresses.
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It shall contain all maps needing a non-default address.
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Possible map names are:
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"main", "dpll", "cp", "hdmi", "edid", "repeater",
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"infoframe", "cbus", "cec", "sdp", "txa", "txb"
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The device node must contain one 'port' child node per device input and output
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port, in accordance with the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
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are numbered as follows.
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Name Type Port
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---------------------------------------
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AIN0 sink 0
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AIN1 sink 1
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AIN2 sink 2
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AIN3 sink 3
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AIN4 sink 4
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AIN5 sink 5
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AIN6 sink 6
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AIN7 sink 7
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HDMI sink 8
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TTL sink 9
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TXA source 10
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TXB source 11
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The digital output port nodes, when present, shall contain at least one
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endpoint. Each of those endpoints shall contain the data-lanes property as
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described in video-interfaces.txt.
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Required source endpoint properties:
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- data-lanes: an array of physical data lane indexes
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The accepted value(s) for this property depends on which of the two
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sources are described. For TXA 1, 2 or 4 data lanes can be described
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while for TXB only 1 data lane is valid. See video-interfaces.txt
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for detailed description.
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Ports are optional if they are not connected to anything at the hardware level.
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Example:
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video-receiver@70 {
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compatible = "adi,adv7482";
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reg = <0x70 0x71 0x72 0x73 0x74 0x75
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0x60 0x61 0x62 0x63 0x64 0x65>;
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reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
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"infoframe", "cbus", "cec", "sdp", "txa", "txb";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&gpio6>;
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interrupt-names = "intrq1", "intrq2";
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interrupts = <30 IRQ_TYPE_LEVEL_LOW>,
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<31 IRQ_TYPE_LEVEL_LOW>;
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port@7 {
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reg = <7>;
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adv7482_ain7: endpoint {
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remote-endpoint = <&cvbs_in>;
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};
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};
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port@8 {
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reg = <8>;
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adv7482_hdmi: endpoint {
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remote-endpoint = <&hdmi_in>;
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};
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};
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port@a {
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reg = <10>;
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adv7482_txa: endpoint {
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clock-lanes = <0>;
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data-lanes = <1 2 3 4>;
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remote-endpoint = <&csi40_in>;
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};
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};
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port@b {
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reg = <11>;
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adv7482_txb: endpoint {
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clock-lanes = <0>;
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data-lanes = <1>;
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remote-endpoint = <&csi20_in>;
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};
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};
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};
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