/*
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* (C) Copyright 2014
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* Gabriel Huau <contact@huau-gabriel.fr>
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <linux/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/imx-regs.h>
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#define MAX_CPUS 4
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static struct src *src = (struct src *)SRC_BASE_ADDR;
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static uint32_t cpu_reset_mask[MAX_CPUS] = {
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0, /* We don't really want to modify the cpu0 */
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SRC_SCR_CORE_1_RESET_MASK,
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SRC_SCR_CORE_2_RESET_MASK,
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SRC_SCR_CORE_3_RESET_MASK
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};
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static uint32_t cpu_ctrl_mask[MAX_CPUS] = {
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0, /* We don't really want to modify the cpu0 */
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SRC_SCR_CORE_1_ENABLE_MASK,
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SRC_SCR_CORE_2_ENABLE_MASK,
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SRC_SCR_CORE_3_ENABLE_MASK
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};
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int cpu_reset(int nr)
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{
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/* Software reset of the CPU N */
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src->scr |= cpu_reset_mask[nr];
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return 0;
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}
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int cpu_status(int nr)
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{
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printf("core %d => %d\n", nr, !!(src->scr & cpu_ctrl_mask[nr]));
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return 0;
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}
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int cpu_release(int nr, int argc, char *const argv[])
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{
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uint32_t boot_addr;
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boot_addr = simple_strtoul(argv[0], NULL, 16);
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switch (nr) {
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case 1:
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src->gpr3 = boot_addr;
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break;
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case 2:
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src->gpr5 = boot_addr;
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break;
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case 3:
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src->gpr7 = boot_addr;
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break;
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default:
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return 1;
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}
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/* CPU N is ready to start */
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src->scr |= cpu_ctrl_mask[nr];
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return 0;
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}
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int is_core_valid(unsigned int core)
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{
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uint32_t nr_cores = get_nr_cpus();
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if (core > nr_cores)
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return 0;
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return 1;
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}
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int cpu_disable(int nr)
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{
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/* Disable the CPU N */
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src->scr &= ~cpu_ctrl_mask[nr];
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return 0;
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}
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