/*
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* Copyright (c) 2015 South Silicon Valley Microelectronics Inc.
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* Copyright (c) 2015 iComm Corporation
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _SDIO_DEF_H_
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#define _SDIO_DEF_H_
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#include <linux/scatterlist.h>
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#define BASE_SDIO 0
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#define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00)
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#define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01)
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#define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02)
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#define REG_INT_MASK (BASE_SDIO + 0x04)
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#define REG_INT_STATUS (BASE_SDIO + 0x08)
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#define REG_INT_TRIGGER (BASE_SDIO + 0x09)
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#define REG_Fn1_STATUS (BASE_SDIO + 0x0c)
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#define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10)
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#define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11)
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#define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12)
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#define REG_CARD_SELF_TEST (BASE_SDIO + 0x13)
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#define REG_CARD_RCA_0 (BASE_SDIO + 0x20)
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#define REG_CARD_RCA_1 (BASE_SDIO + 0x21)
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#define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24)
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#define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25)
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#define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55)
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#define REG_PMU_WAKEUP (BASE_SDIO + 0x67)
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#define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70)
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#define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71)
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#define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72)
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#define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98)
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#define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99)
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#define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a)
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#define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c)
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#define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d)
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#define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e)
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#if 0
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#define SDIO_TX_ALLOC_SUCCESS 0x01
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#define SDIO_TX_NO_ALLOC 0x02
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#define SDIO_TX_DULPICATE_ALLOC 0x04
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#define SDIO_TX_TX_DONE 0x08
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#define SDIO_TX_AHB_HANG 0x10
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#define SDIO_TX_MB_FULL 0x80
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#define SDIO_HCI_IN_QUEUE_EMPTY 0x04
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#define SDIO_EDCA0_SHIFT 4
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#define SDIO_TX_ALLOC_SIZE_SHIFT 0x07
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#define SDIO_TX_ALLOC_ENABLE 0x10
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#endif
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#define SDIO_DEF_BLOCK_SIZE 0x80
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#if (SDIO_DEF_BLOCK_SIZE % 8)
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#error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
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#endif
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#define SDIO_DEF_OUTPUT_TIMING 0
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#define SDIO_DEF_BLOCK_MODE_THRD 128
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#if (SDIO_DEF_BLOCK_MODE_THRD % 8)
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#error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!!
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#endif
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#define SDIO_DEF_FORCE_BLOCK_MODE 0
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#define MAX_SCATTER_ENTRIES_PER_REQ 8
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struct sdio_scatter_item {
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u8 *buf;
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int len;
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};
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struct sdio_scatter_req {
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u32 req;
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u32 len;
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int scat_entries;
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struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ];
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struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
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};
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#define SDIO_READ 0x00000001
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#define SDIO_WRITE 0x00000002
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#define CMD53_ARG_READ 0
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#define CMD53_ARG_WRITE 1
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#define CMD53_ARG_BLOCK_BASIS 1
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#define CMD53_ARG_FIXED_ADDRESS 0
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#define CMD53_ARG_INCR_ADDRESS 1
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#ifdef CONFIG_FW_ALIGNMENT_CHECK
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#define SDIO_DMA_BUFFER_LEN 2048
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#endif
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#ifdef CONFIG_PM
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#define SDIO_COMMAND_BUFFER_LEN 256
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#endif
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#endif
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