/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8822B_SUPPORT == 1)
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void phydm_dynamic_switch_htstf_mumimo_8822b(struct dm_struct *dm)
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{
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u8 rssi_l2h = 40, rssi_h2l = 35;
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/*@if Pin > -60dBm, enable HT-STF gain controller, otherwise, if rssi < -65dBm, disable the controller*/
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if (dm->rssi_min >= rssi_l2h)
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odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x1);
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else if (dm->rssi_min < rssi_h2l)
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odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
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}
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void phydm_dynamic_parameters_ota(struct dm_struct *dm)
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{
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u8 rssi_l2h = 40, rssi_h2l = 35;
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/* PD TH modify due to enlarge MF windows size */
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odm_set_bb_reg(dm, 0x838, 0xf0, 0x6);
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if ((*dm->channel <= 14) && (*dm->band_width == CHANNEL_WIDTH_20)) {
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if (dm->rssi_min >= rssi_l2h) {
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/*@if (dm->bhtstfdisabled == false)*/
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odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x1);
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odm_set_bb_reg(dm, R_0x98c, 0x7fc0000, 0x0);
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odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x1);
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odm_set_bb_reg(dm, R_0xc04, BIT(18), 0x0);
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odm_set_bb_reg(dm, R_0xe04, BIT(18), 0x0);
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if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) {
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odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0x444);
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odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0x4444aaaa);
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} else if (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B) {
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odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0x444);
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odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0x444444aa);
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}
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} else if (dm->rssi_min < rssi_h2l) {
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/*@if (dm->bhtstfdisabled == true)*/
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odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
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odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
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odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x4);
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odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
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odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
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odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0xaaa);
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odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0xaaaaaaaa);
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}
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} else {
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#if 0
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//odm_set_bb_reg(dm, R_0x8d8, BIT(17), 0x0);
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#endif
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odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
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odm_set_bb_reg(dm, R_0x818, 0x7000000, 0x4);
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odm_set_bb_reg(dm, R_0xc04, (BIT(18) | BIT(21)), 0x0);
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odm_set_bb_reg(dm, R_0xe04, (BIT(18) | BIT(21)), 0x0);
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odm_set_bb_reg(dm, R_0x19d8, MASKDWORD, 0xaaa);
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odm_set_bb_reg(dm, R_0x19d4, MASKDWORD, 0xaaaaaaaa);
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}
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}
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static void
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_set_tx_a_cali_value(
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struct dm_struct *dm,
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enum rf_path rf_path,
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u8 offset,
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u8 tx_a_bias_offset)
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{
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u32 modi_tx_a_value = 0;
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u8 tmp1_byte = 0;
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boolean is_minus = false;
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u8 comp_value = 0;
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switch (offset) {
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case 0x0:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10124);
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break;
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case 0x1:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10524);
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break;
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case 0x2:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10924);
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break;
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case 0x3:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X10D24);
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break;
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case 0x4:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30164);
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break;
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case 0x5:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30564);
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break;
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case 0x6:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30964);
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break;
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case 0x7:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X30D64);
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break;
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case 0x8:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50195);
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break;
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case 0x9:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50595);
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break;
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case 0xa:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50995);
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break;
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case 0xb:
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odm_set_rf_reg(dm, rf_path, RF_0x18, 0xFFFFF, 0X50D95);
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break;
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default:
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PHYDM_DBG(dm, ODM_COMP_API, "Invalid TxA band offset...\n");
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return;
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}
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/* @Get TxA value */
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modi_tx_a_value = odm_get_rf_reg(dm, rf_path, RF_0x61, 0xFFFFF);
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tmp1_byte = (u8)modi_tx_a_value & (BIT(3) | BIT(2) | BIT(1) | BIT(0));
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/* @check how much need to calibration */
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switch (tx_a_bias_offset) {
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case 0xF6:
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is_minus = true;
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comp_value = 3;
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break;
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case 0xF4:
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is_minus = true;
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comp_value = 2;
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break;
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case 0xF2:
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is_minus = true;
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comp_value = 1;
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break;
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case 0xF3:
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is_minus = false;
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comp_value = 1;
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break;
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case 0xF5:
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is_minus = false;
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comp_value = 2;
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break;
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case 0xF7:
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is_minus = false;
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comp_value = 3;
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break;
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case 0xF9:
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is_minus = false;
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comp_value = 4;
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break;
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/* @do nothing case */
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case 0xF0:
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default:
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PHYDM_DBG(dm, ODM_COMP_API,
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"No need to do TxA bias current calibration\n");
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return;
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}
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/* @calc correct value to calibrate */
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if (is_minus) {
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if (tmp1_byte >= comp_value)
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tmp1_byte -= comp_value;
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#if 0
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//modi_tx_a_value += tmp1_byte;
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#endif
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else
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tmp1_byte = 0;
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} else {
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tmp1_byte += comp_value;
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if (tmp1_byte >= 7)
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tmp1_byte = 7;
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}
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/* Write back to RF reg */
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odm_set_rf_reg(dm, rf_path, RF_0x30, 0xFFFF, (offset << 12 | (modi_tx_a_value & 0xFF0) | tmp1_byte));
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}
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static void
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_txa_bias_cali_4_each_path(
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struct dm_struct *dm,
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u8 rf_path,
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u8 efuse_value)
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{
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/* switch on set TxA bias */
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odm_set_rf_reg(dm, rf_path, RF_0xef, 0xFFFFF, 0x200);
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/* Set 12 sets of TxA value */
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x0, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x1, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x2, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x3, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x4, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x5, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x6, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x7, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x8, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0x9, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xa, efuse_value);
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_set_tx_a_cali_value(dm, (enum rf_path)rf_path, 0xb, efuse_value);
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/* switch off set TxA bias */
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odm_set_rf_reg(dm, rf_path, RF_0xef, 0xFFFFF, 0x0);
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}
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/* @for 8822B PCIE D-cut patch only */
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/* Normal driver and MP driver need this patch */
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void phydm_txcurrentcalibration(struct dm_struct *dm)
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{
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u8 efuse0x3D8, efuse0x3D7;
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u32 orig_rf0x18_path_a = 0, orig_rf0x18_path_b = 0;
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if (!(dm->support_ic_type & ODM_RTL8822B))
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return;
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PHYDM_DBG(dm, ODM_COMP_API,
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"8822b 5g tx current calibration 0x3d7=0x%X 0x3d8=0x%X\n",
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dm->efuse0x3d7, dm->efuse0x3d8);
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/* save original 0x18 value */
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orig_rf0x18_path_a = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, 0xFFFFF);
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orig_rf0x18_path_b = odm_get_rf_reg(dm, RF_PATH_B, RF_0x18, 0xFFFFF);
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/* @define efuse content */
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efuse0x3D8 = dm->efuse0x3d8;
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efuse0x3D7 = dm->efuse0x3d7;
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/* @check efuse content to judge whether need to calibration or not */
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if (efuse0x3D7 == 0xFF) {
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PHYDM_DBG(dm, ODM_COMP_API,
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"efuse content 0x3D7 == 0xFF, No need to do TxA cali\n");
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return;
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}
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/* write RF register for calibration */
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_txa_bias_cali_4_each_path(dm, RF_PATH_A, efuse0x3D7);
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_txa_bias_cali_4_each_path(dm, RF_PATH_B, efuse0x3D8);
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/* restore original 0x18 value */
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odm_set_rf_reg(dm, RF_PATH_A, RF_0x18, 0xFFFFF, orig_rf0x18_path_a);
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odm_set_rf_reg(dm, RF_PATH_B, RF_0x18, 0xFFFFF, orig_rf0x18_path_b);
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}
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void phydm_1rcca_setting(struct dm_struct *dm, boolean enable_1rcca)
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{
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u32 reg_32;
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reg_32 = odm_get_bb_reg(dm, R_0xa04, 0x0f000000);
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/* @Enable or disable 1RCCA setting accrodding to the control from driver */
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if (enable_1rcca) {
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if (reg_32 == 0x0)
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/* @CCK path-a */
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odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x13);
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else if (reg_32 == 0x5)
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/* @CCK path-b */
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odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x23);
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} else {
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if (dm->valid_path_set == BB_PATH_A) {
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/* @disable 1RCCA */
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/* @CCK default is at path-a */
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odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x31);
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
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} else if (dm->valid_path_set == BB_PATH_B) {
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/* @disable 1RCCA */
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/* @CCK default is at path-a */
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odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x32);
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5);
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} else {
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/* @disable 1RCCA */
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/* @CCK default is at path-a */
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odm_set_bb_reg(dm, R_0x808, MASKBYTE0, 0x33);
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0);
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}
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}
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}
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void phydm_dynamic_select_cck_path_8822b(struct dm_struct *dm)
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{
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struct phydm_fa_struct *fa_cnt = (struct phydm_fa_struct *)phydm_get_structure(dm, PHYDM_FALSEALMCNT);
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struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
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if (dm->ap_total_num > 10) {
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if (drp_8822b->path_judge & BIT(2))
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /*@fix CCK Path A if AP nums > 10*/
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return;
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}
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if (drp_8822b->path_judge & BIT(2))
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return;
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PHYDM_DBG(dm, ODM_PHY_CONFIG,
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"phydm 8822b cck rx path selection start\n");
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if (drp_8822b->path_judge & BB_PATH_A) {
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drp_8822b->path_a_cck_fa = (u16)fa_cnt->cnt_cck_fail;
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drp_8822b->path_judge &= ~BB_PATH_A;
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@change to path B collect CCKFA*/
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} else if (drp_8822b->path_judge & BB_PATH_B) {
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drp_8822b->path_b_cck_fa = (u16)fa_cnt->cnt_cck_fail;
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drp_8822b->path_judge &= ~BB_PATH_B;
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if (drp_8822b->path_a_cck_fa <= drp_8822b->path_b_cck_fa)
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x0); /*@FA A<=B choose A*/
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else
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odm_set_bb_reg(dm, R_0xa04, 0x0f000000, 0x5); /*@FA B>A choose B*/
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drp_8822b->path_judge |= BIT(2); /*@it means we have already choosed cck rx path*/
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}
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PHYDM_DBG(dm, ODM_PHY_CONFIG, "path_a_fa = %d, path_b_fa = %d\n",
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drp_8822b->path_a_cck_fa, drp_8822b->path_b_cck_fa);
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}
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void phydm_somlrxhp_setting(struct dm_struct *dm, boolean switch_soml)
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{
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if (switch_soml) {
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odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0xd90a0000);
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/* @Following are RxHP settings for T2R as always low, workaround for OTA test, required to classify */
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} else {
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odm_set_bb_reg(dm, R_0x19a8, MASKDWORD, 0x090a0000);
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}
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/* @Dynamic RxHP setting with SoML on/off apply on all RFE type */
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if (!switch_soml && (dm->rfe_type == 1 || dm->rfe_type == 6 || dm->rfe_type == 7 || dm->rfe_type == 9)) {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
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}
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if (*dm->channel <= 14) {
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if (switch_soml && (!(dm->rfe_type == 3 || dm->rfe_type == 5 || dm->rfe_type == 8 || dm->rfe_type == 17))) {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
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}
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} else if (*dm->channel > 35) {
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if (switch_soml) {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
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}
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}
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/* @for 8822B RXHP H2L, since always L will cause DFS FRD */
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if (dm->is_dfs_band) {
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odm_set_bb_reg(dm, 0x8d8, MASKDWORD, 0x29035612);
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odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x08108492);
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}
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#if 0
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if (!(dm->rfe_type == 1 || dm->rfe_type == 6 || dm->rfe_type == 7 || dm->rfe_type == 9)) {
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if (*dm->channel <= 14) {
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/* TFBGA iFEM SoML on/off with RxHP always high-to-low */
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if (switch_soml == true && (!(dm->rfe_type == 3 || dm->rfe_type == 5))) {
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if (switch_soml == true) {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
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odm_set_bb_reg(dm, R_0xc04, (BIT(21) | (BIT(18))), 0x0);
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odm_set_bb_reg(dm, R_0xe04, (BIT(21) | (BIT(18))), 0x0);
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} else {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108492);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
|
}
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}
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} else if (*dm->channel > 35) {
|
if (switch_soml == true) {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108000);
|
odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x0);
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odm_set_bb_reg(dm, R_0xc04, (BIT(21) | (BIT(18))), 0x0);
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odm_set_bb_reg(dm, R_0xe04, (BIT(21) | (BIT(18))), 0x0);
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} else {
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odm_set_bb_reg(dm, R_0x8cc, MASKDWORD, 0x08108492);
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odm_set_bb_reg(dm, R_0x8d8, BIT(27), 0x1);
|
}
|
}
|
PHYDM_DBG(dm, ODM_COMP_API,
|
"Dynamic RxHP control with SoML is enable !!\n");
|
}
|
#endif
|
}
|
|
void phydm_config_tx2path_8822b(struct dm_struct *dm,
|
enum wireless_set wireless_mode,
|
boolean is_tx2_path)
|
{
|
if (wireless_mode == WIRELESS_CCK) {
|
if (is_tx2_path)
|
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0xc);
|
else
|
odm_set_bb_reg(dm, R_0xa04, 0xf0000000, 0x8);
|
} else {
|
if (is_tx2_path)
|
odm_set_bb_reg(dm, R_0x93c, 0xf00000, 0x3);
|
else
|
odm_set_bb_reg(dm, R_0x93c, 0xf00000, 0x1);
|
}
|
}
|
|
#ifdef DYN_ANT_WEIGHTING_SUPPORT
|
void phydm_dynamic_ant_weighting_8822b(void *dm_void)
|
{
|
struct dm_struct *dm = (struct dm_struct *)dm_void;
|
u8 rssi_l2h = 43, rssi_h2l = 37;
|
u8 reg_8;
|
|
if (dm->is_disable_dym_ant_weighting)
|
return;
|
#ifdef CONFIG_MCC_DM
|
if (dm->is_stop_dym_ant_weighting)
|
return;
|
#endif
|
if (*dm->channel <= 14) {
|
if (dm->rssi_min >= rssi_l2h) {
|
odm_set_bb_reg(dm, R_0x98c, 0x7fc0000, 0x0);
|
|
/*@equal weighting*/
|
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
|
PHYDM_DBG(dm, ODM_COMP_API,
|
"Equal weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
|
dm->rssi_min, reg_8);
|
} else if (dm->rssi_min <= rssi_h2l) {
|
odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
|
|
/*@fix sec_min_wgt = 1/2*/
|
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
|
PHYDM_DBG(dm, ODM_COMP_API,
|
"AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
|
dm->rssi_min, reg_8);
|
}
|
} else {
|
odm_set_bb_reg(dm, R_0x98c, MASKDWORD, 0x43440000);
|
|
reg_8 = (u8)odm_get_bb_reg(dm, R_0xf94, BIT(0) | BIT(1) | BIT(2));
|
PHYDM_DBG(dm, ODM_COMP_API,
|
"AGC weighting ,rssi_min = %d\n, 0xf94[2:0] = 0x%x\n",
|
dm->rssi_min, reg_8);
|
/*@fix sec_min_wgt = 1/2*/
|
}
|
}
|
#endif
|
|
|
#ifdef CONFIG_DYNAMIC_BYPASS
|
void
|
phydm_pw_sat_8822b(
|
struct dm_struct *dm,
|
u8 rssi_value
|
)
|
{
|
u8 ret=2;
|
|
if (dm->rfe_type != 2)
|
return;
|
|
/* check */
|
ret = odm_get_bb_reg(dm, 0xcb0, BIT(9));
|
|
/* apply on eFEM type*/
|
if (rssi_value >= 75) {
|
if (*dm->p_channel > 35) {
|
if (ret == 0) {
|
PHYDM_DBG(dm, ODM_PHY_CONFIG,
|
("Already in bypass mode setting\n"));
|
return;
|
}
|
odm_set_bb_reg(dm, 0x8cc, MASKDWORD, 0x8108000);
|
odm_set_bb_reg(dm, 0x8d8, BIT(27), 0x0);
|
odm_set_bb_reg(dm, 0x840, BIT(12), 0x1);
|
odm_set_bb_reg(dm, 0x810, (BIT(24)|BIT(25)), 0x2);
|
odm_set_bb_reg(dm, 0x814, BIT(0), 0x1);
|
odm_set_bb_reg(dm, 0x844, BIT(24), 0x1);
|
|
odm_set_bb_reg(dm, 0x830, MASKDWORD, 0x79a0eaaa);
|
odm_set_bb_reg(dm, 0xe58, BIT(20), 0x1);
|
|
odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
|
0x177717);
|
odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
|
0x177717);
|
odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x77);
|
odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x77);
|
|
PHYDM_DBG(dm, ODM_PHY_CONFIG,
|
("External-fem turn off !!\n"));
|
|
phydm_rxagc_switch_8822b(dm, true);
|
}
|
} else if (rssi_value <= 55) {
|
if (*dm->p_channel > 35) {
|
if (ret == 1) {
|
PHYDM_DBG(dm, ODM_PHY_CONFIG,
|
("Not in bypass mode setting\n"));
|
return;
|
}
|
odm_set_bb_reg(dm, 0xcb0, (MASKBYTE2 | MASKLWORD),
|
0x177517);
|
odm_set_bb_reg(dm, 0xeb0, (MASKBYTE2 | MASKLWORD),
|
0x177517);
|
odm_set_bb_reg(dm, 0xcb4, MASKBYTE1, 0x75);
|
odm_set_bb_reg(dm, 0xeb4, MASKBYTE1, 0x75);
|
|
PHYDM_DBG(dm, ODM_PHY_CONFIG,
|
("External-fem turn on !!rssi =%d\n", rssi_value));
|
|
phydm_rxagc_switch_8822b(dm, false);
|
}
|
}
|
}
|
#endif
|
|
void phydm_hwsetting_8822b(struct dm_struct *dm)
|
{
|
struct drp_rtl8822b_struct *drp_8822b = &dm->phydm_rtl8822b;
|
u8 set_result_nbi = PHYDM_SET_NO_NEED;
|
|
if ((dm->p_advance_ota & PHYDM_HP_OTA_SETTING_A) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_B)) {
|
phydm_dynamic_parameters_ota(dm);
|
} else {
|
if (!dm->bhtstfdisabled)
|
phydm_dynamic_switch_htstf_mumimo_8822b(dm);
|
else
|
PHYDM_DBG(dm, ODM_PHY_CONFIG,
|
"Default HT-STF gain control setting\n");
|
}
|
|
phydm_dynamic_ant_weighting(dm);
|
|
if (dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) {
|
/* PD TH modify due to enlarge MF windows size */
|
odm_set_bb_reg(dm, 0x838, 0xf0, 0x6);
|
|
if (dm->rssi_min <= 20)
|
phydm_somlrxhp_setting(dm, false);
|
else if (dm->rssi_min >= 25)
|
phydm_somlrxhp_setting(dm, true);
|
}
|
|
if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING_CCK_PATH) || (dm->p_advance_ota & PHYDM_HP_OTA_SETTING_CCK_PATH)) {
|
if (dm->is_linked)
|
phydm_dynamic_select_cck_path_8822b(dm);
|
else
|
drp_8822b->path_judge |= ((~BIT(2)) | BB_PATH_A | BB_PATH_B);
|
}
|
|
if (dm->p_advance_ota & PHYDM_LENOVO_OTA_SETTING_NBI_CSI) {
|
if ((*dm->band_width == CHANNEL_WIDTH_80) && (*dm->channel == 157)) {
|
set_result_nbi = phydm_nbi_setting(dm, FUNC_ENABLE, *dm->channel, 80, 5760, PHYDM_DONT_CARE);
|
PHYDM_DBG(dm, ODM_PHY_CONFIG, "Enable NBI\n");
|
}
|
}
|
}
|
|
#endif /* RTL8822B_SUPPORT == 1 */
|
