/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#ifndef _I40E_DCB_H_
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#define _I40E_DCB_H_
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#include "i40e_type.h"
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#define I40E_DCBX_STATUS_IN_PROGRESS 1
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#define I40E_DCBX_STATUS_DONE 2
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#define I40E_DCBX_STATUS_DISABLED 7
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#define I40E_TLV_TYPE_END 0
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#define I40E_TLV_TYPE_ORG 127
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#define I40E_IEEE_8021QAZ_OUI 0x0080C2
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#define I40E_IEEE_SUBTYPE_ETS_CFG 9
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#define I40E_IEEE_SUBTYPE_ETS_REC 10
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#define I40E_IEEE_SUBTYPE_PFC_CFG 11
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#define I40E_IEEE_SUBTYPE_APP_PRI 12
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#define I40E_CEE_DCBX_OUI 0x001b21
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#define I40E_CEE_DCBX_TYPE 2
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#define I40E_CEE_SUBTYPE_PG_CFG 2
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#define I40E_CEE_SUBTYPE_PFC_CFG 3
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#define I40E_CEE_SUBTYPE_APP_PRI 4
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#define I40E_CEE_MAX_FEAT_TYPE 3
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#define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET 0x2B
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#define I40E_LLDP_CURRENT_STATUS_X722_OFFSET 0x31
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#define I40E_LLDP_CURRENT_STATUS_OFFSET 1
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#define I40E_LLDP_CURRENT_STATUS_SIZE 1
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/* Defines for LLDP TLV header */
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#define I40E_LLDP_TLV_LEN_SHIFT 0
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#define I40E_LLDP_TLV_LEN_MASK (0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
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#define I40E_LLDP_TLV_TYPE_SHIFT 9
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#define I40E_LLDP_TLV_TYPE_MASK (0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
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#define I40E_LLDP_TLV_SUBTYPE_SHIFT 0
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#define I40E_LLDP_TLV_SUBTYPE_MASK (0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
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#define I40E_LLDP_TLV_OUI_SHIFT 8
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#define I40E_LLDP_TLV_OUI_MASK (0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
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/* Defines for IEEE ETS TLV */
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#define I40E_IEEE_ETS_MAXTC_SHIFT 0
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#define I40E_IEEE_ETS_MAXTC_MASK (0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
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#define I40E_IEEE_ETS_CBS_SHIFT 6
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#define I40E_IEEE_ETS_CBS_MASK BIT(I40E_IEEE_ETS_CBS_SHIFT)
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#define I40E_IEEE_ETS_WILLING_SHIFT 7
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#define I40E_IEEE_ETS_WILLING_MASK BIT(I40E_IEEE_ETS_WILLING_SHIFT)
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#define I40E_IEEE_ETS_PRIO_0_SHIFT 0
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#define I40E_IEEE_ETS_PRIO_0_MASK (0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
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#define I40E_IEEE_ETS_PRIO_1_SHIFT 4
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#define I40E_IEEE_ETS_PRIO_1_MASK (0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
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#define I40E_CEE_PGID_PRIO_0_SHIFT 0
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#define I40E_CEE_PGID_PRIO_0_MASK (0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
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#define I40E_CEE_PGID_PRIO_1_SHIFT 4
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#define I40E_CEE_PGID_PRIO_1_MASK (0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
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#define I40E_CEE_PGID_STRICT 15
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/* Defines for IEEE TSA types */
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#define I40E_IEEE_TSA_STRICT 0
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#define I40E_IEEE_TSA_ETS 2
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/* Defines for IEEE PFC TLV */
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#define I40E_IEEE_PFC_CAP_SHIFT 0
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#define I40E_IEEE_PFC_CAP_MASK (0xF << I40E_IEEE_PFC_CAP_SHIFT)
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#define I40E_IEEE_PFC_MBC_SHIFT 6
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#define I40E_IEEE_PFC_MBC_MASK BIT(I40E_IEEE_PFC_MBC_SHIFT)
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#define I40E_IEEE_PFC_WILLING_SHIFT 7
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#define I40E_IEEE_PFC_WILLING_MASK BIT(I40E_IEEE_PFC_WILLING_SHIFT)
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/* Defines for IEEE APP TLV */
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#define I40E_IEEE_APP_SEL_SHIFT 0
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#define I40E_IEEE_APP_SEL_MASK (0x7 << I40E_IEEE_APP_SEL_SHIFT)
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#define I40E_IEEE_APP_PRIO_SHIFT 5
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#define I40E_IEEE_APP_PRIO_MASK (0x7 << I40E_IEEE_APP_PRIO_SHIFT)
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#pragma pack(1)
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/* IEEE 802.1AB LLDP Organization specific TLV */
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struct i40e_lldp_org_tlv {
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__be16 typelength;
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__be32 ouisubtype;
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u8 tlvinfo[1];
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};
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struct i40e_cee_tlv_hdr {
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__be16 typelen;
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u8 operver;
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u8 maxver;
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};
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struct i40e_cee_ctrl_tlv {
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struct i40e_cee_tlv_hdr hdr;
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__be32 seqno;
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__be32 ackno;
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};
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struct i40e_cee_feat_tlv {
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struct i40e_cee_tlv_hdr hdr;
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u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
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#define I40E_CEE_FEAT_TLV_WILLING_MASK 0x40
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u8 subtype;
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u8 tlvinfo[1];
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};
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struct i40e_cee_app_prio {
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__be16 protocol;
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u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
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#define I40E_CEE_APP_SELECTOR_MASK 0x03
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__be16 lower_oui;
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u8 prio_map;
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};
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#pragma pack()
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i40e_status i40e_get_dcbx_status(struct i40e_hw *hw,
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u16 *status);
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i40e_status i40e_lldp_to_dcb_config(u8 *lldpmib,
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struct i40e_dcbx_config *dcbcfg);
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i40e_status i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
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u8 bridgetype,
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struct i40e_dcbx_config *dcbcfg);
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i40e_status i40e_get_dcb_config(struct i40e_hw *hw);
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i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change);
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#endif /* _I40E_DCB_H_ */
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