/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright 2017 IBM Corp.
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#ifndef _OCXL_INTERNAL_H_
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#define _OCXL_INTERNAL_H_
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#include <linux/pci.h>
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#include <linux/cdev.h>
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#include <linux/list.h>
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#include <misc/ocxl.h>
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#define MAX_IRQ_PER_LINK 2000
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#define MAX_IRQ_PER_CONTEXT MAX_IRQ_PER_LINK
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extern struct pci_driver ocxl_pci_driver;
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struct ocxl_fn {
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struct device dev;
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int bar_used[3];
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struct ocxl_fn_config config;
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struct list_head afu_list;
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int pasid_base;
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int actag_base;
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int actag_enabled;
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int actag_supported;
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struct list_head pasid_list;
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struct list_head actag_list;
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void *link;
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};
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struct ocxl_file_info {
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struct ocxl_afu *afu;
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struct device dev;
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struct cdev cdev;
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struct bin_attribute attr_global_mmio;
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};
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struct ocxl_afu {
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struct kref kref;
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struct ocxl_fn *fn;
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struct list_head list;
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struct ocxl_afu_config config;
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int pasid_base;
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int pasid_count; /* opened contexts */
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int pasid_max; /* maximum number of contexts */
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int actag_base;
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int actag_enabled;
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struct mutex contexts_lock;
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struct idr contexts_idr;
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struct mutex afu_control_lock;
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u64 global_mmio_start;
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u64 irq_base_offset;
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void __iomem *global_mmio_ptr;
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u64 pp_mmio_start;
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void *private;
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};
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enum ocxl_context_status {
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CLOSED,
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OPENED,
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ATTACHED,
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};
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// Contains metadata about a translation fault
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struct ocxl_xsl_error {
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u64 addr; // The address that triggered the fault
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u64 dsisr; // the value of the dsisr register
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u64 count; // The number of times this fault has been triggered
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};
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struct ocxl_context {
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struct ocxl_afu *afu;
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int pasid;
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struct mutex status_mutex;
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enum ocxl_context_status status;
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struct address_space *mapping;
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struct mutex mapping_lock;
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wait_queue_head_t events_wq;
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struct mutex xsl_error_lock;
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struct ocxl_xsl_error xsl_error;
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struct mutex irq_lock;
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struct idr irq_idr;
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u16 tidr; // Thread ID used for P9 wait implementation
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};
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struct ocxl_process_element {
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__be64 config_state;
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__be32 reserved1[11];
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__be32 lpid;
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__be32 tid;
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__be32 pid;
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__be32 reserved2[10];
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__be64 amr;
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__be32 reserved3[3];
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__be32 software_state;
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};
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int ocxl_create_cdev(struct ocxl_afu *afu);
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void ocxl_destroy_cdev(struct ocxl_afu *afu);
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int ocxl_file_register_afu(struct ocxl_afu *afu);
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void ocxl_file_unregister_afu(struct ocxl_afu *afu);
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int ocxl_file_init(void);
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void ocxl_file_exit(void);
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int ocxl_pasid_afu_alloc(struct ocxl_fn *fn, u32 size);
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void ocxl_pasid_afu_free(struct ocxl_fn *fn, u32 start, u32 size);
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int ocxl_actag_afu_alloc(struct ocxl_fn *fn, u32 size);
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void ocxl_actag_afu_free(struct ocxl_fn *fn, u32 start, u32 size);
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/*
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* Get the max PASID value that can be used by the function
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*/
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int ocxl_config_get_pasid_info(struct pci_dev *dev, int *count);
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/*
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* Control whether the FPGA is reloaded on a link reset
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*/
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int ocxl_config_get_reset_reload(struct pci_dev *dev, int *val);
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int ocxl_config_set_reset_reload(struct pci_dev *dev, int val);
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/*
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* Check if an AFU index is valid for the given function.
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*
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* AFU indexes can be sparse, so a driver should check all indexes up
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* to the maximum found in the function description
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*/
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int ocxl_config_check_afu_index(struct pci_dev *dev,
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struct ocxl_fn_config *fn, int afu_idx);
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/**
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* ocxl_link_update_pe() - Update values within a Process Element
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* @link_handle: the link handle associated with the process element
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* @pasid: the PASID for the AFU context
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* @tid: the new thread id for the process element
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*
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* Returns 0 on success
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*/
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int ocxl_link_update_pe(void *link_handle, int pasid, __u16 tid);
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int ocxl_context_mmap(struct ocxl_context *ctx,
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struct vm_area_struct *vma);
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void ocxl_context_detach_all(struct ocxl_afu *afu);
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int ocxl_sysfs_register_afu(struct ocxl_file_info *info);
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void ocxl_sysfs_unregister_afu(struct ocxl_file_info *info);
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int ocxl_irq_offset_to_id(struct ocxl_context *ctx, u64 offset);
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u64 ocxl_irq_id_to_offset(struct ocxl_context *ctx, int irq_id);
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void ocxl_afu_irq_free_all(struct ocxl_context *ctx);
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#endif /* _OCXL_INTERNAL_H_ */
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