/* SPDX-License-Identifier: GPL-2.0 */
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/*****************************************************************************/
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/*
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* head.S -- common startup code for ColdFire CPUs.
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*
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* (C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
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*/
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/*****************************************************************************/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/asm-offsets.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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#include <asm/mcfmmu.h>
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#include <asm/thread_info.h>
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/*****************************************************************************/
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/*
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* If we don't have a fixed memory size, then lets build in code
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* to auto detect the DRAM size. Obviously this is the preferred
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* method, and should work for most boards. It won't work for those
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* that do not have their RAM starting at address 0, and it only
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* works on SDRAM (not boards fitted with SRAM).
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*/
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#if CONFIG_RAMSIZE != 0
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.macro GET_MEM_SIZE
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movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */
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.endm
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#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
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defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
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defined(CONFIG_M5307) || defined(CONFIG_M5407)
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/*
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* Not all these devices have exactly the same DRAM controller,
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* but the DCMR register is virtually identical - give or take
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* a couple of bits. The only exception is the 5272 devices, their
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* DRAM controller is quite different.
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*/
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.macro GET_MEM_SIZE
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movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */
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btst #0,%d0 /* check if region enabled */
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beq 1f
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andl #0xfffc0000,%d0
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beq 1f
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addl #0x00040000,%d0 /* convert mask to size */
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1:
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movel MCFSIM_DMR1,%d1 /* get mask for 2nd bank */
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btst #0,%d1 /* check if region enabled */
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beq 2f
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andl #0xfffc0000,%d1
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beq 2f
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addl #0x00040000,%d1
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addl %d1,%d0 /* total mem size in d0 */
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2:
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.endm
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#elif defined(CONFIG_M5272)
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.macro GET_MEM_SIZE
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movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */
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andil #0xfffff000,%d0 /* mask out chip select options */
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negl %d0 /* negate bits */
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.endm
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#elif defined(CONFIG_M520x)
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.macro GET_MEM_SIZE
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clrl %d0
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movel MCFSIM_SDCS0, %d2 /* Get SDRAM chip select 0 config */
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andl #0x1f, %d2 /* Get only the chip select size */
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beq 3f /* Check if it is enabled */
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addql #1, %d2 /* Form exponent */
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moveql #1, %d0
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lsll %d2, %d0 /* 2 ^ exponent */
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3:
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movel MCFSIM_SDCS1, %d2 /* Get SDRAM chip select 1 config */
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andl #0x1f, %d2 /* Get only the chip select size */
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beq 4f /* Check if it is enabled */
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addql #1, %d2 /* Form exponent */
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moveql #1, %d1
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lsll %d2, %d1 /* 2 ^ exponent */
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addl %d1, %d0 /* Total size of SDRAM in d0 */
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4:
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.endm
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#else
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#error "ERROR: I don't know how to probe your boards memory size?"
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#endif
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/*****************************************************************************/
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/*
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* Boards and platforms can do specific early hardware setup if
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* they need to. Most don't need this, define away if not required.
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*/
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#ifndef PLATFORM_SETUP
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#define PLATFORM_SETUP
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#endif
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/*****************************************************************************/
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.global _start
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.global _rambase
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.global _ramvec
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.global _ramstart
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.global _ramend
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#if defined(CONFIG_UBOOT)
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.global _init_sp
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#endif
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/*****************************************************************************/
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.data
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/*
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* During startup we store away the RAM setup. These are not in the
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* bss, since their values are determined and written before the bss
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* has been cleared.
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*/
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_rambase:
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.long 0
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_ramvec:
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.long 0
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_ramstart:
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.long 0
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_ramend:
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.long 0
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#if defined(CONFIG_UBOOT)
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_init_sp:
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.long 0
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#endif
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/*****************************************************************************/
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__HEAD
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#ifdef CONFIG_MMU
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_start0:
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jmp _start
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.global kernel_pg_dir
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.equ kernel_pg_dir,_start0
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.equ .,_start0+0x1000
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#endif
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/*
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* This is the codes first entry point. This is where it all
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* begins...
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*/
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_start:
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nop /* filler */
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movew #0x2700, %sr /* no interrupts */
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movel #CACHE_INIT,%d0 /* disable cache */
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movec %d0,%CACR
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nop
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#if defined(CONFIG_UBOOT)
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movel %sp,_init_sp /* save initial stack pointer */
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#endif
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#ifdef CONFIG_MBAR
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movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */
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movec %d0,%MBAR /* set it */
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#endif
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/*
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* Do any platform or board specific setup now. Most boards
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* don't need anything. Those exceptions are define this in
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* their board specific includes.
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*/
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PLATFORM_SETUP
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/*
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* Create basic memory configuration. Set VBR accordingly,
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* and size memory.
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*/
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movel #CONFIG_VECTORBASE,%a7
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movec %a7,%VBR /* set vectors addr */
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movel %a7,_ramvec
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movel #CONFIG_RAMBASE,%a7 /* mark the base of RAM */
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movel %a7,_rambase
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GET_MEM_SIZE /* macro code determines size */
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addl %a7,%d0
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movel %d0,_ramend /* set end ram addr */
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/*
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* Now that we know what the memory is, lets enable cache
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* and get things moving. This is Coldfire CPU specific. Not
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* all version cores have identical cache register setup. But
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* it is very similar. Define the exact settings in the headers
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* then the code here is the same for all.
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*/
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movel #ACR0_MODE,%d0 /* set RAM region for caching */
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movec %d0,%ACR0
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movel #ACR1_MODE,%d0 /* anything else to cache? */
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movec %d0,%ACR1
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#ifdef ACR2_MODE
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movel #ACR2_MODE,%d0
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movec %d0,%ACR2
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movel #ACR3_MODE,%d0
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movec %d0,%ACR3
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#endif
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movel #CACHE_MODE,%d0 /* enable cache */
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movec %d0,%CACR
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nop
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#ifdef CONFIG_MMU
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/*
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* Identity mapping for the kernel region.
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*/
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movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */
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movec %d0,%MMUBAR
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movel #MMUOR_CA,%d0 /* clear TLB entries */
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movel %d0,MMUOR
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movel #0,%d0 /* set ASID to 0 */
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movec %d0,%asid
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movel #MMUCR_EN,%d0 /* Enable the identity map */
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movel %d0,MMUCR
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nop /* sync i-pipeline */
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movel #_vstart,%a0 /* jump to "virtual" space */
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jmp %a0@
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_vstart:
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#endif /* CONFIG_MMU */
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#ifdef CONFIG_ROMFS_FS
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/*
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* Move ROM filesystem above bss :-)
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*/
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lea __bss_start,%a0 /* get start of bss */
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lea __bss_stop,%a1 /* set up destination */
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movel %a0,%a2 /* copy of bss start */
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movel 8(%a0),%d0 /* get size of ROMFS */
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addql #8,%d0 /* allow for rounding */
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andl #0xfffffffc, %d0 /* whole words */
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addl %d0,%a0 /* copy from end */
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addl %d0,%a1 /* copy from end */
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movel %a1,_ramstart /* set start of ram */
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_copy_romfs:
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movel -(%a0),%d0 /* copy dword */
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movel %d0,-(%a1)
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cmpl %a0,%a2 /* check if at end */
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bne _copy_romfs
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#else /* CONFIG_ROMFS_FS */
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lea __bss_stop,%a1
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movel %a1,_ramstart
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#endif /* CONFIG_ROMFS_FS */
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/*
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* Zero out the bss region.
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*/
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lea __bss_start,%a0 /* get start of bss */
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lea __bss_stop,%a1 /* get end of bss */
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clrl %d0 /* set value */
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_clear_bss:
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movel %d0,(%a0)+ /* clear each word */
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cmpl %a0,%a1 /* check if at end */
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bne _clear_bss
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/*
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* Load the current task pointer and stack.
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*/
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lea init_thread_union,%a0
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lea THREAD_SIZE(%a0),%sp
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#ifdef CONFIG_MMU
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.global m68k_cputype
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.global m68k_mmutype
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.global m68k_fputype
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.global m68k_machtype
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movel #CPU_COLDFIRE,%d0
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movel %d0,m68k_cputype /* Mark us as a ColdFire */
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movel #MMU_COLDFIRE,%d0
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movel %d0,m68k_mmutype
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movel #FPUTYPE,%d0
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movel %d0,m68k_fputype /* Mark FPU type */
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movel #MACHINE,%d0
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movel %d0,m68k_machtype /* Mark machine type */
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lea init_task,%a2 /* Set "current" init task */
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#endif
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/*
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* Assembler start up done, start code proper.
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*/
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jsr start_kernel /* start Linux kernel */
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_exit:
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jmp _exit /* should never get here */
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/*****************************************************************************/
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