/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_HASH_H
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#define _ASM_HASH_H
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/*
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* The later H8SX models have a 32x32-bit multiply, but the H8/300H
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* and H8S have only 16x16->32. Since it's tolerably compact, this is
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* basically an inlined version of the __mulsi3 code. Since the inputs
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* are not expected to be small, it's also simplfied by skipping the
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* early-out checks.
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*
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* (Since neither CPU has any multi-bit shift instructions, a
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* shift-and-add version is a non-starter.)
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*
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* TODO: come up with an arch-specific version of the hashing in fs/namei.c,
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* since that is heavily dependent on rotates. Which, as mentioned, suck
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* horribly on H8.
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*/
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#if defined(CONFIG_CPU_H300H) || defined(CONFIG_CPU_H8S)
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#define HAVE_ARCH__HASH_32 1
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/*
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* Multiply by k = 0x61C88647. Fitting this into three registers requires
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* one extra instruction, but reducing register pressure will probably
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* make that back and then some.
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*
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* GCC asm note: %e1 is the high half of operand %1, while %f1 is the
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* low half. So if %1 is er4, then %e1 is e4 and %f1 is r4.
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*
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* This has been designed to modify x in place, since that's the most
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* common usage, but preserve k, since hash_64() makes two calls in
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* quick succession.
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*/
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static inline u32 __attribute_const__ __hash_32(u32 x)
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{
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u32 temp;
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asm( "mov.w %e1,%f0"
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"\n mulxu.w %f2,%0" /* klow * xhigh */
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"\n mov.w %f0,%e1" /* The extra instruction */
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"\n mov.w %f1,%f0"
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"\n mulxu.w %e2,%0" /* khigh * xlow */
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"\n add.w %e1,%f0"
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"\n mulxu.w %f2,%1" /* klow * xlow */
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"\n add.w %f0,%e1"
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: "=&r" (temp), "=r" (x)
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: "%r" (GOLDEN_RATIO_32), "1" (x));
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return x;
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}
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#endif
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#endif /* _ASM_HASH_H */
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