// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/memory/rk3399-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr3_speed_bin = <21>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_lp_dis_freq = <666>;
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ddr3_dll_dis_freq = <300>;
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phy_dll_dis_freq = <260>;
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ddr3_odt_dis_freq = <666>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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phy_ddr3_odt = <PHY_DRV_ODT_240>;
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lpddr3_odt_dis_freq = <666>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>;
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phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>;
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phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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lpddr4_odt_dis_freq = <800>;
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lpddr4_drv = <LP4_PDDS_240ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_DIS>;
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phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_40>;
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phy_lpddr4_dq_drv = <PHY_DRV_ODT_60>;
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phy_lpddr4_odt = <PHY_DRV_ODT_40>;
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};
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};
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