// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2017 Marvell Technology Group Ltd.
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*
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* Device Tree file for the Armada 70x0 SoC
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*/
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/ {
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aliases {
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gpio1 = &cp0_gpio1;
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gpio2 = &cp0_gpio2;
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spi1 = &cp0_spi0;
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spi2 = &cp0_spi1;
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};
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};
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/*
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* Instantiate the CP110
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*/
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#define CP11X_NAME cp0
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#define CP11X_BASE f2000000
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#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
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#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
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#define CP11X_PCIE0_BASE f2600000
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#define CP11X_PCIE1_BASE f2620000
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#define CP11X_PCIE2_BASE f2640000
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#include "armada-cp110.dtsi"
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#undef CP11X_NAME
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#undef CP11X_BASE
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#undef CP11X_PCIEx_MEM_BASE
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#undef CP11X_PCIEx_MEM_SIZE
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#undef CP11X_PCIE0_BASE
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#undef CP11X_PCIE1_BASE
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#undef CP11X_PCIE2_BASE
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&cp0_gpio1 {
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status = "okay";
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};
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&cp0_gpio2 {
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status = "okay";
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};
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&cp0_syscon0 {
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cp0_pinctrl: pinctrl {
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compatible = "marvell,armada-7k-pinctrl";
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nand_pins: nand-pins {
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marvell,pins =
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"mpp15", "mpp16", "mpp17", "mpp18",
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"mpp19", "mpp20", "mpp21", "mpp22",
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"mpp23", "mpp24", "mpp25", "mpp26",
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"mpp27";
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marvell,function = "dev";
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};
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nand_rb: nand-rb {
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marvell,pins = "mpp13";
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marvell,function = "nf";
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};
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};
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};
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