/* SPDX-License-Identifier: GPL-2.0
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*
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* include/asm-sh/cpu-sh2/watchdog.h
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*
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* Copyright (C) 2002, 2003 Paul Mundt
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*/
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#ifndef __ASM_CPU_SH2_WATCHDOG_H
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#define __ASM_CPU_SH2_WATCHDOG_H
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/*
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* More SH-2 brilliance .. its not good enough that we can't read
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* and write the same sizes to WTCNT, now we have to read and write
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* with different sizes at different addresses for WTCNT _and_ RSTCSR.
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*
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* At least on the bright side no one has managed to screw over WTCSR
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* in this fashion .. yet.
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*/
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/* Register definitions */
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#define WTCNT 0xfffffe80
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#define WTCSR 0xfffffe80
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#define RSTCSR 0xfffffe82
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#define WTCNT_R (WTCNT + 1)
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#define RSTCSR_R (RSTCSR + 1)
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/* Bit definitions */
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#define WTCSR_IOVF 0x80
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#define WTCSR_WT 0x40
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#define WTCSR_TME 0x20
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#define WTCSR_RSTS 0x00
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#define RSTCSR_RSTS 0x20
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/**
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* sh_wdt_read_rstcsr - Read from Reset Control/Status Register
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*
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* Reads back the RSTCSR value.
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*/
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static inline __u8 sh_wdt_read_rstcsr(void)
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{
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/*
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* Same read/write brain-damage as for WTCNT here..
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*/
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return __raw_readb(RSTCSR_R);
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}
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/**
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* sh_wdt_write_csr - Write to Reset Control/Status Register
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*
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* @val: Value to write
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*
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* Writes the given value @val to the lower byte of the control/status
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* register. The upper byte is set manually on each write.
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*/
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static inline void sh_wdt_write_rstcsr(__u8 val)
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{
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/*
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* Note: Due to the brain-damaged nature of this register,
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* we can't presently touch the WOVF bit, since the upper byte
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* has to be swapped for this. So just leave it alone..
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*/
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__raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
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}
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#endif /* __ASM_CPU_SH2_WATCHDOG_H */
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