// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3588-vehicle-evb-v21.dtsi"
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#include "rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi"
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#include "rk3588-vehicle-serdes-mfd-display-rohm.dtsi"
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#include "rk3588-android.dtsi"
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/ {
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model = "Rockchip RK3588 VEHICLE EVB V21 Board";
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compatible = "rockchip,rk3588-vehicle-evb-v21", "rockchip,rk3588";
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bt-sound {
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compatible = "simple-audio-card";
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simple-audio-card,format = "dsp_a";
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simple-audio-card,bitclock-inversion = <1>;
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simple-audio-card,mclk-fs = <256>;
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simple-audio-card,name = "rockchip,bt";
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simple-audio-card,cpu {
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sound-dai = <&i2s2_2ch>;
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};
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simple-audio-card,codec {
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sound-dai = <&bt_sco 1>;
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};
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};
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bt_sco: bt-sco {
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compatible = "delta,dfbmcs320";
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#sound-dai-cells = <1>;
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status = "okay";
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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reverse {
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label = "GPIO Key Reverse";
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linux,code = <KEY_CAMERA_DOWN>;
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gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
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debounce-interval = <100>;
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};
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park {
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label = "GPIO Key Park";
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linux,code = <KEY_CAMERA>;
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gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
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debounce-interval = <100>;
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};
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};
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};
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&i2c2 {
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himax@48 {
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himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&i2c4 {
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himax@48 {
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himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&i2c5 {
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ilitek@41 {
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interrupt-parent = <&gpio0>;
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interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
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reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>;
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};
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};
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&i2c6 {
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himax@48 {
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himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>; //use rst as int
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};
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};
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&i2s2_2ch {
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pinctrl-0 = <&i2s2m1_lrck
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&i2s2m1_sclk
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&i2s2m1_sdi
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&i2s2m1_sdo>;
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status = "okay";
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};
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&pinctrl {
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bl {
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bl0_enable_pin: bl0-enable-pin {
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rockchip,pins =
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<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
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<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
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<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bl1_enable_pin: bl1-enable-pin {
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rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bl2_enable_pin: bl2-enable-pin {
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rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bl3_enable_pin: bl3-enable-pin {
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rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bl4_enable_pin: bl4-enable-pin {
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rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bl5_enable_pin: bl5-enable-pin {
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rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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serdes {
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//dsi0
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ser0_rst_pin: ser0-rst-pin {
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rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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//dsi1
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ser1_rst_pin: ser1-rst-pin {
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rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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touch {
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//dsi0-i2c2
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touch_gpio_dsi0: touch-gpio-dsi0 {
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rockchip,pins =
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<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //rst
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};
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//dsi1-i2c6
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touch_gpio_dsi1: touch-gpio-dsi1 {
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rockchip,pins =
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<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, //rst
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<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; //int
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};
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//dp0-i2c4
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touch_gpio_dp0: touch-gpio-dp0 {
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rockchip,pins =
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<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, //rst
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<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; //int
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};
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//edp0-i2c5
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touch_gpio_edp0: touch-gpio-edp0 {
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rockchip,pins =
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<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, //rst
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<0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; //int
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};
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};
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};
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&rockchip_suspend {
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rockchip,sleep-mode-config = <
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(0
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| RKPM_SLP_ARMOFF_DDRPD
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| RKPM_SLP_PMU_PMUALIVE_32K
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| RKPM_SLP_PMU_DIS_OSC
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| RKPM_SLP_32K_EXT
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)
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>;
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rockchip,wakeup-config = <
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(0
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| RKPM_CPU0_WKUP_EN
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| RKPM_GPIO_WKUP_EN
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)
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>;
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status = "okay";
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};
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&vdd_log_s0 {
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <800000>;
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};
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};
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&vcc_3v3_s0 {
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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&vcc_1v8_s0 {
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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&vdd_1v8_pll_s0 {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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