// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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#include "rk3562-evb2-ddr4-v10.dtsi"
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#include "rk3562-android.dtsi"
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#include "rk3562-rk809.dtsi"
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/ {
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model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board";
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compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562";
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};
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&dsi {
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status = "disabled";
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};
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&dsi_in_vp0 {
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status = "disabled";
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};
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/*
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* The pins of gamc0 and bt1120 are multiplexed
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*/
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&gmac0 {
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status = "disabled";
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-0 = <&i2c1m1_xfer>;
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status = "okay";
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sii9022: sii9022@39 {
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compatible = "sil,sii9022";
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reg = <0x39>;
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pinctrl-names = "default";
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pinctrl-0 = <&sii902x_hdmi_int>;
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interrupt-parent = <&gpio4>;
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interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
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enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
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/*
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* MEDIA_BUS_FMT_YUYV8_1X16 for bt1120
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* MEDIA_BUS_FMT_UYVY8_2X8 for bt656
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*/
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bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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sii9022_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_sii9022>;
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};
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};
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};
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};
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};
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&pinctrl {
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sii902x {
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sii902x_hdmi_int: sii902x-hdmi-int {
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rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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&rgb {
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status = "okay";
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pinctrl-names = "default";
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/*
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* <&bt1120_pins> for bt1120
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* <&bt656_pins> for bt656
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*/
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pinctrl-0 = <&bt1120_pins>;
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ports {
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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rgb_out_sii9022: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&sii9022_in_rgb>;
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};
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};
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};
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};
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&rgb_in_vp0 {
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status = "okay";
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};
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&video_phy {
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status = "disabled";
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};
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