/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_TYPE_H_
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#define _ICE_TYPE_H_
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#define ICE_BYTES_PER_WORD 2
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#define ICE_BYTES_PER_DWORD 4
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#include "ice_status.h"
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#include "ice_hw_autogen.h"
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#include "ice_osdep.h"
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#include "ice_controlq.h"
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#include "ice_lan_tx_rx.h"
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#include "ice_flex_type.h"
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#include "ice_protocol_type.h"
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static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
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{
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return test_bit(tc, &bitmap);
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}
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static inline u64 round_up_64bit(u64 a, u32 b)
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{
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return div64_long(((a) + (b) / 2), (b));
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}
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static inline u32 ice_round_to_num(u32 N, u32 R)
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{
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return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
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((((N) + (R) - 1) / (R)) * (R)));
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}
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/* Driver always calls main vsi_handle first */
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#define ICE_MAIN_VSI_HANDLE 0
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/* debug masks - set these bits in hw->debug_mask to control output */
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#define ICE_DBG_INIT BIT_ULL(1)
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#define ICE_DBG_FW_LOG BIT_ULL(3)
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#define ICE_DBG_LINK BIT_ULL(4)
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#define ICE_DBG_PHY BIT_ULL(5)
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#define ICE_DBG_QCTX BIT_ULL(6)
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#define ICE_DBG_NVM BIT_ULL(7)
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#define ICE_DBG_LAN BIT_ULL(8)
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#define ICE_DBG_FLOW BIT_ULL(9)
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#define ICE_DBG_SW BIT_ULL(13)
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#define ICE_DBG_SCHED BIT_ULL(14)
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#define ICE_DBG_PKG BIT_ULL(16)
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#define ICE_DBG_RES BIT_ULL(17)
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#define ICE_DBG_AQ_MSG BIT_ULL(24)
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#define ICE_DBG_AQ_DESC BIT_ULL(25)
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#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
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#define ICE_DBG_AQ_CMD BIT_ULL(27)
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#define ICE_DBG_USER BIT_ULL(31)
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enum ice_aq_res_ids {
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ICE_NVM_RES_ID = 1,
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ICE_SPD_RES_ID,
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ICE_CHANGE_LOCK_RES_ID,
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ICE_GLOBAL_CFG_LOCK_RES_ID
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};
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/* FW update timeout definitions are in milliseconds */
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#define ICE_NVM_TIMEOUT 180000
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#define ICE_CHANGE_LOCK_TIMEOUT 1000
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#define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
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enum ice_aq_res_access_type {
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ICE_RES_READ = 1,
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ICE_RES_WRITE
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};
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struct ice_driver_ver {
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u8 major_ver;
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u8 minor_ver;
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u8 build_ver;
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u8 subbuild_ver;
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u8 driver_string[32];
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};
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enum ice_fc_mode {
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ICE_FC_NONE = 0,
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ICE_FC_RX_PAUSE,
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ICE_FC_TX_PAUSE,
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ICE_FC_FULL,
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ICE_FC_PFC,
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ICE_FC_DFLT
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};
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enum ice_phy_cache_mode {
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ICE_FC_MODE = 0,
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ICE_SPEED_MODE,
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ICE_FEC_MODE
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};
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enum ice_fec_mode {
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ICE_FEC_NONE = 0,
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ICE_FEC_RS,
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ICE_FEC_BASER,
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ICE_FEC_AUTO
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};
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struct ice_phy_cache_mode_data {
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union {
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enum ice_fec_mode curr_user_fec_req;
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enum ice_fc_mode curr_user_fc_req;
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u16 curr_user_speed_req;
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} data;
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};
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enum ice_set_fc_aq_failures {
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ICE_SET_FC_AQ_FAIL_NONE = 0,
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ICE_SET_FC_AQ_FAIL_GET,
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ICE_SET_FC_AQ_FAIL_SET,
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ICE_SET_FC_AQ_FAIL_UPDATE
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};
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/* Various MAC types */
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enum ice_mac_type {
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ICE_MAC_UNKNOWN = 0,
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ICE_MAC_E810,
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ICE_MAC_GENERIC,
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};
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/* Media Types */
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enum ice_media_type {
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ICE_MEDIA_UNKNOWN = 0,
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ICE_MEDIA_FIBER,
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ICE_MEDIA_BASET,
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ICE_MEDIA_BACKPLANE,
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ICE_MEDIA_DA,
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};
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enum ice_vsi_type {
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ICE_VSI_PF = 0,
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ICE_VSI_VF = 1,
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ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
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ICE_VSI_LB = 6,
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};
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struct ice_link_status {
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/* Refer to ice_aq_phy_type for bits definition */
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u64 phy_type_low;
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u64 phy_type_high;
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u8 topo_media_conflict;
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u16 max_frame_size;
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u16 link_speed;
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u16 req_speeds;
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u8 lse_ena; /* Link Status Event notification */
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u8 link_info;
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u8 an_info;
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u8 ext_info;
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u8 fec_info;
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u8 pacing;
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/* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
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* ice_aqc_get_phy_caps structure
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*/
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u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
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};
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/* Different reset sources for which a disable queue AQ call has to be made in
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* order to clean the Tx scheduler as a part of the reset
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*/
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enum ice_disq_rst_src {
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ICE_NO_RESET = 0,
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ICE_VM_RESET,
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ICE_VF_RESET,
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};
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/* PHY info such as phy_type, etc... */
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struct ice_phy_info {
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struct ice_link_status link_info;
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struct ice_link_status link_info_old;
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u64 phy_type_low;
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u64 phy_type_high;
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enum ice_media_type media_type;
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u8 get_link_info;
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/* Please refer to struct ice_aqc_get_link_status_data to get
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* detail of enable bit in curr_user_speed_req
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*/
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u16 curr_user_speed_req;
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enum ice_fec_mode curr_user_fec_req;
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enum ice_fc_mode curr_user_fc_req;
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struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
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};
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/* protocol enumeration for filters */
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enum ice_fltr_ptype {
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/* NONE - used for undef/error */
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ICE_FLTR_PTYPE_NONF_NONE = 0,
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ICE_FLTR_PTYPE_NONF_IPV4_UDP,
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ICE_FLTR_PTYPE_NONF_IPV4_TCP,
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ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
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ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
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ICE_FLTR_PTYPE_FRAG_IPV4,
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ICE_FLTR_PTYPE_NONF_IPV6_UDP,
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ICE_FLTR_PTYPE_NONF_IPV6_TCP,
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ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
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ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
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ICE_FLTR_PTYPE_MAX,
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};
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enum ice_fd_hw_seg {
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ICE_FD_HW_SEG_NON_TUN = 0,
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ICE_FD_HW_SEG_TUN,
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ICE_FD_HW_SEG_MAX,
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};
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/* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */
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#define ICE_MAX_FDIR_VSI_PER_FILTER 2
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struct ice_fd_hw_prof {
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struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
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int cnt;
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u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
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u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
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};
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/* Common HW capabilities for SW use */
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struct ice_hw_common_caps {
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u32 valid_functions;
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/* DCB capabilities */
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u32 active_tc_bitmap;
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u32 maxtc;
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/* Tx/Rx queues */
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u16 num_rxq; /* Number/Total Rx queues */
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u16 rxq_first_id; /* First queue ID for Rx queues */
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u16 num_txq; /* Number/Total Tx queues */
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u16 txq_first_id; /* First queue ID for Tx queues */
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/* MSI-X vectors */
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u16 num_msix_vectors;
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u16 msix_vector_first_id;
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/* Max MTU for function or device */
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u16 max_mtu;
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/* Virtualization support */
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u8 sr_iov_1_1; /* SR-IOV enabled */
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/* RSS related capabilities */
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u16 rss_table_size; /* 512 for PFs and 64 for VFs */
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u8 rss_table_entry_width; /* RSS Entry width in bits */
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u8 dcb;
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bool nvm_update_pending_nvm;
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bool nvm_update_pending_orom;
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bool nvm_update_pending_netlist;
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#define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
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#define ICE_NVM_PENDING_OROM BIT(1)
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#define ICE_NVM_PENDING_NETLIST BIT(2)
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bool nvm_unified_update;
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#define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
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};
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/* Function specific capabilities */
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struct ice_hw_func_caps {
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struct ice_hw_common_caps common_cap;
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u32 num_allocd_vfs; /* Number of allocated VFs */
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u32 vf_base_id; /* Logical ID of the first VF */
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u32 guar_num_vsi;
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u32 fd_fltr_guar; /* Number of filters guaranteed */
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u32 fd_fltr_best_effort; /* Number of best effort filters */
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};
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/* Device wide capabilities */
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struct ice_hw_dev_caps {
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struct ice_hw_common_caps common_cap;
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u32 num_vfs_exposed; /* Total number of VFs exposed */
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u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
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u32 num_flow_director_fltr; /* Number of FD filters available */
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u32 num_funcs;
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};
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/* MAC info */
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struct ice_mac_info {
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u8 lan_addr[ETH_ALEN];
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u8 perm_addr[ETH_ALEN];
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};
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/* Reset types used to determine which kind of reset was requested. These
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* defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
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* ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
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* because its reset source is different than the other types listed.
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*/
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enum ice_reset_req {
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ICE_RESET_POR = 0,
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ICE_RESET_INVAL = 0,
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ICE_RESET_CORER = 1,
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ICE_RESET_GLOBR = 2,
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ICE_RESET_EMPR = 3,
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ICE_RESET_PFR = 4,
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};
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/* Bus parameters */
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struct ice_bus_info {
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u16 device;
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u8 func;
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};
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/* Flow control (FC) parameters */
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struct ice_fc_info {
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enum ice_fc_mode current_mode; /* FC mode in effect */
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enum ice_fc_mode req_mode; /* FC mode requested by caller */
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};
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/* Option ROM version information */
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struct ice_orom_info {
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u8 major; /* Major version of OROM */
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u8 patch; /* Patch version of OROM */
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u16 build; /* Build version of OROM */
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};
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/* NVM Information */
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struct ice_nvm_info {
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struct ice_orom_info orom; /* Option ROM version info */
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u32 eetrack; /* NVM data version */
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u16 sr_words; /* Shadow RAM size in words */
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u32 flash_size; /* Size of available flash in bytes */
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u8 major_ver; /* major version of NVM package */
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u8 minor_ver; /* minor version of dev starter */
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u8 blank_nvm_mode; /* is NVM empty (no FW present) */
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};
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struct ice_link_default_override_tlv {
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u8 options;
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#define ICE_LINK_OVERRIDE_OPT_M 0x3F
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#define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
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#define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
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#define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
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#define ICE_LINK_OVERRIDE_EN BIT(3)
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#define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
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#define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
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u8 phy_config;
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#define ICE_LINK_OVERRIDE_PHY_CFG_S 8
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#define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
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#define ICE_LINK_OVERRIDE_PAUSE_M 0x3
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#define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
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#define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
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u8 fec_options;
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#define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
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u8 rsvd1;
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u64 phy_type_low;
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u64 phy_type_high;
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};
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#define ICE_NVM_VER_LEN 32
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/* netlist version information */
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struct ice_netlist_ver_info {
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u32 major; /* major high/low */
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u32 minor; /* minor high/low */
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u32 type; /* type high/low */
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u32 rev; /* revision high/low */
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u32 hash; /* SHA-1 hash word */
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u16 cust_ver; /* customer version */
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};
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/* Max number of port to queue branches w.r.t topology */
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#define ICE_MAX_TRAFFIC_CLASS 8
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#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
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#define ice_for_each_traffic_class(_i) \
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for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
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#define ICE_INVAL_TEID 0xFFFFFFFF
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struct ice_sched_node {
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struct ice_sched_node *parent;
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struct ice_sched_node *sibling; /* next sibling in the same layer */
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struct ice_sched_node **children;
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struct ice_aqc_txsched_elem_data info;
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u32 agg_id; /* aggregator group ID */
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u16 vsi_handle;
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u8 in_use; /* suspended or in use */
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u8 tx_sched_layer; /* Logical Layer (1-9) */
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u8 num_children;
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u8 tc_num;
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u8 owner;
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#define ICE_SCHED_NODE_OWNER_LAN 0
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};
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/* Access Macros for Tx Sched Elements data */
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#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
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/* The aggregator type determines if identifier is for a VSI group,
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* aggregator group, aggregator of queues, or queue group.
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*/
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enum ice_agg_type {
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ICE_AGG_TYPE_UNKNOWN = 0,
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ICE_AGG_TYPE_VSI,
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ICE_AGG_TYPE_AGG, /* aggregator */
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ICE_AGG_TYPE_Q,
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ICE_AGG_TYPE_QG
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};
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/* Rate limit types */
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enum ice_rl_type {
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ICE_UNKNOWN_BW = 0,
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ICE_MIN_BW, /* for CIR profile */
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ICE_MAX_BW, /* for EIR profile */
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ICE_SHARED_BW /* for shared profile */
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};
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#define ICE_SCHED_MIN_BW 500 /* in Kbps */
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#define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
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#define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
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#define ICE_SCHED_DFLT_RL_PROF_ID 0
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#define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
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#define ICE_SCHED_DFLT_BW_WT 4
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#define ICE_SCHED_INVAL_PROF_ID 0xFFFF
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#define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
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/* Data structure for saving BW information */
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enum ice_bw_type {
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ICE_BW_TYPE_PRIO,
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ICE_BW_TYPE_CIR,
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ICE_BW_TYPE_CIR_WT,
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ICE_BW_TYPE_EIR,
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ICE_BW_TYPE_EIR_WT,
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ICE_BW_TYPE_SHARED,
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ICE_BW_TYPE_CNT /* This must be last */
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};
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struct ice_bw {
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u32 bw;
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u16 bw_alloc;
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};
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struct ice_bw_type_info {
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DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
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u8 generic;
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struct ice_bw cir_bw;
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struct ice_bw eir_bw;
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u32 shared_bw;
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};
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/* VSI queue context structure for given TC */
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struct ice_q_ctx {
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u16 q_handle;
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u32 q_teid;
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/* bw_t_info saves queue BW information */
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struct ice_bw_type_info bw_t_info;
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};
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/* VSI type list entry to locate corresponding VSI/aggregator nodes */
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struct ice_sched_vsi_info {
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struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
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struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
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struct list_head list_entry;
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u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
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};
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/* driver defines the policy */
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struct ice_sched_tx_policy {
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u16 max_num_vsis;
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u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
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u8 rdma_ena;
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};
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/* CEE or IEEE 802.1Qaz ETS Configuration data */
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struct ice_dcb_ets_cfg {
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u8 willing;
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u8 cbs;
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u8 maxtcs;
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u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
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u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
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u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
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};
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/* CEE or IEEE 802.1Qaz PFC Configuration data */
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struct ice_dcb_pfc_cfg {
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u8 willing;
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u8 mbc;
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u8 pfccap;
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u8 pfcena;
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};
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/* CEE or IEEE 802.1Qaz Application Priority data */
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struct ice_dcb_app_priority_table {
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u16 prot_id;
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u8 priority;
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u8 selector;
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};
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#define ICE_MAX_USER_PRIORITY 8
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#define ICE_DCBX_MAX_APPS 32
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#define ICE_LLDPDU_SIZE 1500
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#define ICE_TLV_STATUS_OPER 0x1
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#define ICE_TLV_STATUS_SYNC 0x2
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#define ICE_TLV_STATUS_ERR 0x4
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#define ICE_APP_PROT_ID_FCOE 0x8906
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#define ICE_APP_PROT_ID_ISCSI 0x0cbc
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#define ICE_APP_PROT_ID_ISCSI_860 0x035c
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#define ICE_APP_PROT_ID_FIP 0x8914
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#define ICE_APP_SEL_ETHTYPE 0x1
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#define ICE_APP_SEL_TCPIP 0x2
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#define ICE_CEE_APP_SEL_ETHTYPE 0x0
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#define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
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#define ICE_CEE_APP_SEL_TCPIP 0x1
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struct ice_dcbx_cfg {
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u32 numapps;
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u32 tlv_status; /* CEE mode TLV status */
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struct ice_dcb_ets_cfg etscfg;
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struct ice_dcb_ets_cfg etsrec;
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struct ice_dcb_pfc_cfg pfc;
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struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
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u8 dcbx_mode;
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#define ICE_DCBX_MODE_CEE 0x1
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#define ICE_DCBX_MODE_IEEE 0x2
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u8 app_mode;
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#define ICE_DCBX_APPS_NON_WILLING 0x1
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};
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struct ice_qos_cfg {
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struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
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struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
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struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
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u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
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u8 is_sw_lldp : 1;
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};
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struct ice_port_info {
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struct ice_sched_node *root; /* Root Node per Port */
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struct ice_hw *hw; /* back pointer to HW instance */
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u32 last_node_teid; /* scheduler last node info */
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u16 sw_id; /* Initial switch ID belongs to port */
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u16 pf_vf_num;
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u8 port_state;
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#define ICE_SCHED_PORT_STATE_INIT 0x0
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#define ICE_SCHED_PORT_STATE_READY 0x1
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u8 lport;
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#define ICE_LPORT_MASK 0xff
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u16 dflt_tx_vsi_rule_id;
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u16 dflt_tx_vsi_num;
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u16 dflt_rx_vsi_rule_id;
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u16 dflt_rx_vsi_num;
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struct ice_fc_info fc;
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struct ice_mac_info mac;
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struct ice_phy_info phy;
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struct mutex sched_lock; /* protect access to TXSched tree */
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struct ice_sched_node *
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sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
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/* List contain profile ID(s) and other params per layer */
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struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
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struct ice_qos_cfg qos_cfg;
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u8 is_vf:1;
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};
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struct ice_switch_info {
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struct list_head vsi_list_map_head;
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struct ice_sw_recipe *recp_list;
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};
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/* FW logging configuration */
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struct ice_fw_log_evnt {
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u8 cfg : 4; /* New event enables to configure */
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u8 cur : 4; /* Current/active event enables */
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};
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struct ice_fw_log_cfg {
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u8 cq_en : 1; /* FW logging is enabled via the control queue */
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u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
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u8 actv_evnts; /* Cumulation of currently enabled log events */
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#define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
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#define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
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#define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
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#define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
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struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
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};
|
|
/* Port hardware description */
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struct ice_hw {
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u8 __iomem *hw_addr;
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void *back;
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struct ice_aqc_layer_props *layer_info;
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struct ice_port_info *port_info;
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u64 debug_mask; /* bitmap for debug mask */
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enum ice_mac_type mac_type;
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u16 fd_ctr_base; /* FD counter base index */
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/* pci info */
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u16 device_id;
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u16 vendor_id;
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u16 subsystem_device_id;
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u16 subsystem_vendor_id;
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u8 revision_id;
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u8 pf_id; /* device profile info */
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|
u16 max_burst_size; /* driver sets this value */
|
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/* Tx Scheduler values */
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u8 num_tx_sched_layers;
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u8 num_tx_sched_phys_layers;
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u8 flattened_layers;
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u8 max_cgds;
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u8 sw_entry_point_layer;
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u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
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struct list_head agg_list; /* lists all aggregator */
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struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
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u8 evb_veb; /* true for VEB, false for VEPA */
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u8 reset_ongoing; /* true if HW is in reset, false otherwise */
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struct ice_bus_info bus;
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struct ice_nvm_info nvm;
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struct ice_hw_dev_caps dev_caps; /* device capabilities */
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struct ice_hw_func_caps func_caps; /* function capabilities */
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struct ice_netlist_ver_info netlist_ver; /* netlist version info */
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struct ice_switch_info *switch_info; /* switch filter lists */
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/* Control Queue info */
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struct ice_ctl_q_info adminq;
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struct ice_ctl_q_info mailboxq;
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u8 api_branch; /* API branch version */
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u8 api_maj_ver; /* API major version */
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u8 api_min_ver; /* API minor version */
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u8 api_patch; /* API patch version */
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u8 fw_branch; /* firmware branch version */
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u8 fw_maj_ver; /* firmware major version */
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u8 fw_min_ver; /* firmware minor version */
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u8 fw_patch; /* firmware patch version */
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u32 fw_build; /* firmware build number */
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struct ice_fw_log_cfg fw_log;
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|
/* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
|
* register. Used for determining the ITR/INTRL granularity during
|
* initialization.
|
*/
|
#define ICE_MAX_AGG_BW_200G 0x0
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#define ICE_MAX_AGG_BW_100G 0X1
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#define ICE_MAX_AGG_BW_50G 0x2
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#define ICE_MAX_AGG_BW_25G 0x3
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/* ITR granularity for different speeds */
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#define ICE_ITR_GRAN_ABOVE_25 2
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#define ICE_ITR_GRAN_MAX_25 4
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/* ITR granularity in 1 us */
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u8 itr_gran;
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/* INTRL granularity for different speeds */
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#define ICE_INTRL_GRAN_ABOVE_25 4
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#define ICE_INTRL_GRAN_MAX_25 8
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/* INTRL granularity in 1 us */
|
u8 intrl_gran;
|
|
u8 ucast_shared; /* true if VSIs can share unicast addr */
|
|
/* Active package version (currently active) */
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struct ice_pkg_ver active_pkg_ver;
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u32 active_track_id;
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u8 active_pkg_name[ICE_PKG_NAME_SIZE];
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u8 active_pkg_in_nvm;
|
|
enum ice_aq_err pkg_dwnld_status;
|
|
/* Driver's package ver - (from the Metadata seg) */
|
struct ice_pkg_ver pkg_ver;
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u8 pkg_name[ICE_PKG_NAME_SIZE];
|
|
/* Driver's Ice package version (from the Ice seg) */
|
struct ice_pkg_ver ice_pkg_ver;
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u8 ice_pkg_name[ICE_PKG_NAME_SIZE];
|
|
/* Pointer to the ice segment */
|
struct ice_seg *seg;
|
|
/* Pointer to allocated copy of pkg memory */
|
u8 *pkg_copy;
|
u32 pkg_size;
|
|
/* tunneling info */
|
struct mutex tnl_lock;
|
struct ice_tunnel_table tnl;
|
|
struct udp_tunnel_nic_shared udp_tunnel_shared;
|
struct udp_tunnel_nic_info udp_tunnel_nic;
|
|
/* HW block tables */
|
struct ice_blk_info blk[ICE_BLK_COUNT];
|
struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
|
struct list_head fl_profs[ICE_BLK_COUNT];
|
|
/* Flow Director filter info */
|
int fdir_active_fltr;
|
|
struct mutex fdir_fltr_lock; /* protect Flow Director */
|
struct list_head fdir_list_head;
|
|
/* Book-keeping of side-band filter count per flow-type.
|
* This is used to detect and handle input set changes for
|
* respective flow-type.
|
*/
|
u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
|
|
struct ice_fd_hw_prof **fdir_prof;
|
DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
|
struct mutex rss_locks; /* protect RSS configuration */
|
struct list_head rss_list_head;
|
};
|
|
/* Statistics collected by each port, VSI, VEB, and S-channel */
|
struct ice_eth_stats {
|
u64 rx_bytes; /* gorc */
|
u64 rx_unicast; /* uprc */
|
u64 rx_multicast; /* mprc */
|
u64 rx_broadcast; /* bprc */
|
u64 rx_discards; /* rdpc */
|
u64 rx_unknown_protocol; /* rupp */
|
u64 tx_bytes; /* gotc */
|
u64 tx_unicast; /* uptc */
|
u64 tx_multicast; /* mptc */
|
u64 tx_broadcast; /* bptc */
|
u64 tx_discards; /* tdpc */
|
u64 tx_errors; /* tepc */
|
};
|
|
#define ICE_MAX_UP 8
|
|
/* Statistics collected by the MAC */
|
struct ice_hw_port_stats {
|
/* eth stats collected by the port */
|
struct ice_eth_stats eth;
|
/* additional port specific stats */
|
u64 tx_dropped_link_down; /* tdold */
|
u64 crc_errors; /* crcerrs */
|
u64 illegal_bytes; /* illerrc */
|
u64 error_bytes; /* errbc */
|
u64 mac_local_faults; /* mlfc */
|
u64 mac_remote_faults; /* mrfc */
|
u64 rx_len_errors; /* rlec */
|
u64 link_xon_rx; /* lxonrxc */
|
u64 link_xoff_rx; /* lxoffrxc */
|
u64 link_xon_tx; /* lxontxc */
|
u64 link_xoff_tx; /* lxofftxc */
|
u64 priority_xon_rx[8]; /* pxonrxc[8] */
|
u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
|
u64 priority_xon_tx[8]; /* pxontxc[8] */
|
u64 priority_xoff_tx[8]; /* pxofftxc[8] */
|
u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
|
u64 rx_size_64; /* prc64 */
|
u64 rx_size_127; /* prc127 */
|
u64 rx_size_255; /* prc255 */
|
u64 rx_size_511; /* prc511 */
|
u64 rx_size_1023; /* prc1023 */
|
u64 rx_size_1522; /* prc1522 */
|
u64 rx_size_big; /* prc9522 */
|
u64 rx_undersize; /* ruc */
|
u64 rx_fragments; /* rfc */
|
u64 rx_oversize; /* roc */
|
u64 rx_jabber; /* rjc */
|
u64 tx_size_64; /* ptc64 */
|
u64 tx_size_127; /* ptc127 */
|
u64 tx_size_255; /* ptc255 */
|
u64 tx_size_511; /* ptc511 */
|
u64 tx_size_1023; /* ptc1023 */
|
u64 tx_size_1522; /* ptc1522 */
|
u64 tx_size_big; /* ptc9522 */
|
/* flow director stats */
|
u32 fd_sb_status;
|
u64 fd_sb_match;
|
};
|
|
/* Checksum and Shadow RAM pointers */
|
#define ICE_SR_BOOT_CFG_PTR 0x132
|
#define ICE_SR_NVM_WOL_CFG 0x19
|
#define ICE_NVM_OROM_VER_OFF 0x02
|
#define ICE_SR_PBA_BLOCK_PTR 0x16
|
#define ICE_SR_NVM_DEV_STARTER_VER 0x18
|
#define ICE_SR_NVM_EETRACK_LO 0x2D
|
#define ICE_SR_NVM_EETRACK_HI 0x2E
|
#define ICE_NVM_VER_LO_SHIFT 0
|
#define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
|
#define ICE_NVM_VER_HI_SHIFT 12
|
#define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
|
#define ICE_OROM_VER_PATCH_SHIFT 0
|
#define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
|
#define ICE_OROM_VER_BUILD_SHIFT 8
|
#define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
|
#define ICE_OROM_VER_SHIFT 24
|
#define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
|
#define ICE_SR_PFA_PTR 0x40
|
#define ICE_SR_1ST_NVM_BANK_PTR 0x42
|
#define ICE_SR_1ST_OROM_BANK_PTR 0x44
|
#define ICE_SR_NETLIST_BANK_PTR 0x46
|
#define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
|
|
/* Link override related */
|
#define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
|
#define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
|
#define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
|
#define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
|
#define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
|
#define ICE_FW_API_LINK_OVERRIDE_MAJ 1
|
#define ICE_FW_API_LINK_OVERRIDE_MIN 5
|
#define ICE_FW_API_LINK_OVERRIDE_PATCH 2
|
|
#define ICE_SR_WORDS_IN_1KB 512
|
|
/* Hash redirection LUT for VSI - maximum array size */
|
#define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4)
|
|
#endif /* _ICE_TYPE_H_ */
|
