/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef _ICP_QAT_FW_PKE_
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#define _ICP_QAT_FW_PKE_
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#include "icp_qat_fw.h"
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struct icp_qat_fw_req_hdr_pke_cd_pars {
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__u64 content_desc_addr;
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__u32 content_desc_resrvd;
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__u32 func_id;
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};
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struct icp_qat_fw_req_pke_mid {
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__u64 opaque;
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__u64 src_data_addr;
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__u64 dest_data_addr;
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};
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struct icp_qat_fw_req_pke_hdr {
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__u8 resrvd1;
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__u8 resrvd2;
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__u8 service_type;
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__u8 hdr_flags;
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__u16 comn_req_flags;
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__u16 resrvd4;
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struct icp_qat_fw_req_hdr_pke_cd_pars cd_pars;
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};
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struct icp_qat_fw_pke_request {
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struct icp_qat_fw_req_pke_hdr pke_hdr;
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struct icp_qat_fw_req_pke_mid pke_mid;
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__u8 output_param_count;
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__u8 input_param_count;
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__u16 resrvd1;
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__u32 resrvd2;
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__u64 next_req_adr;
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};
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struct icp_qat_fw_resp_pke_hdr {
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__u8 resrvd1;
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__u8 resrvd2;
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__u8 response_type;
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__u8 hdr_flags;
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__u16 comn_resp_flags;
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__u16 resrvd4;
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};
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struct icp_qat_fw_pke_resp {
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struct icp_qat_fw_resp_pke_hdr pke_resp_hdr;
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__u64 opaque;
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__u64 src_data_addr;
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__u64 dest_data_addr;
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};
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#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS 7
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#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK 0x1
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#define ICP_QAT_FW_PKE_RESP_PKE_STAT_GET(status_word) \
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QAT_FIELD_GET(((status_word >> ICP_QAT_FW_COMN_ONE_BYTE_SHIFT) & \
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ICP_QAT_FW_COMN_SINGLE_BYTE_MASK), \
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QAT_COMN_RESP_PKE_STATUS_BITPOS, \
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QAT_COMN_RESP_PKE_STATUS_MASK)
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#define ICP_QAT_FW_PKE_HDR_VALID_FLAG_SET(hdr_t, val) \
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QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
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ICP_QAT_FW_PKE_HDR_VALID_FLAG_BITPOS, \
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ICP_QAT_FW_PKE_HDR_VALID_FLAG_MASK)
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#endif
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