/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef __ICP_QAT_FW_LOADER_HANDLE_H__
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#define __ICP_QAT_FW_LOADER_HANDLE_H__
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#include "icp_qat_uclo.h"
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struct icp_qat_fw_loader_ae_data {
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unsigned int state;
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unsigned int ustore_size;
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unsigned int free_addr;
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unsigned int free_size;
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unsigned int live_ctx_mask;
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};
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struct icp_qat_fw_loader_hal_handle {
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struct icp_qat_fw_loader_ae_data aes[ICP_QAT_UCLO_MAX_AE];
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unsigned int ae_mask;
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unsigned int slice_mask;
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unsigned int revision_id;
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unsigned int ae_max_num;
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unsigned int upc_mask;
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unsigned int max_ustore;
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};
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struct icp_qat_fw_loader_handle {
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struct icp_qat_fw_loader_hal_handle *hal_handle;
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struct pci_dev *pci_dev;
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void *obj_handle;
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void *sobj_handle;
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bool fw_auth;
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void __iomem *hal_sram_addr_v;
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void __iomem *hal_cap_g_ctl_csr_addr_v;
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void __iomem *hal_cap_ae_xfer_csr_addr_v;
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void __iomem *hal_cap_ae_local_csr_addr_v;
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void __iomem *hal_ep_csr_addr_v;
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};
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struct icp_firml_dram_desc {
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void __iomem *dram_base_addr;
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void *dram_base_addr_v;
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dma_addr_t dram_bus_addr;
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u64 dram_size;
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};
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#endif
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