/*
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* Hardware info about DECstation 5000/200 systems (otherwise known as
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* 3max or KN02).
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
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* are by courtesy of Chris Fraser.
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* Copyright (C) 2002, 2003, 2005 Maciej W. Rozycki
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*/
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#ifndef __ASM_MIPS_DEC_KN02_H
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#define __ASM_MIPS_DEC_KN02_H
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#define KN02_SLOT_BASE 0x1fc00000
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#define KN02_SLOT_SIZE 0x00080000
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/*
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* Address ranges decoded by the "system slot" logic for onboard devices.
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*/
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#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
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#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
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#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
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#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
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#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
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#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
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#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
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#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
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/*
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* System Control & Status Register bits.
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*/
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#define KN02_CSR_RES_28 (0xf<<28) /* unused */
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#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
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#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
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#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
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#define KN02_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
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#define KN02_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
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#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
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#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
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#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
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#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
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#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
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#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
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#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
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#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
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#define KN02_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
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#define KN02_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
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/*
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* CPU interrupt bits.
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*/
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#define KN02_CPU_INR_RES_6 6 /* unused */
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#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
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#define KN02_CPU_INR_RES_4 4 /* unused */
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#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
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#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
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/*
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* CSR interrupt bits.
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*/
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#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
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#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
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#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
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#define KN02_CSR_INR_RES_4 4 /* unused */
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#define KN02_CSR_INR_RES_3 3 /* unused */
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#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
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#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
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#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
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#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
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#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
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#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
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#define KN02_IRQ_MASK(n) (1 << (n))
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#define KN02_IRQ_ALL 0xff
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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extern u32 cached_kn02_csr;
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extern void init_kn02_irqs(int base);
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#endif
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#endif /* __ASM_MIPS_DEC_KN02_H */
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