/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_ARC_JUMP_LABEL_H
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#define _ASM_ARC_JUMP_LABEL_H
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#ifndef __ASSEMBLY__
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#include <linux/stringify.h>
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#include <linux/types.h>
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#define JUMP_LABEL_NOP_SIZE 4
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/*
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* NOTE about '.balign 4':
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*
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* To make atomic update of patched instruction available we need to guarantee
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* that this instruction doesn't cross L1 cache line boundary.
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*
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* As of today we simply align instruction which can be patched by 4 byte using
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* ".balign 4" directive. In that case patched instruction is aligned with one
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* 16-bit NOP_S if this is required.
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* However 'align by 4' directive is much stricter than it actually required.
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* It's enough that our 32-bit instruction don't cross L1 cache line boundary /
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* L1 I$ fetch block boundary which can be achieved by using
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* ".bundle_align_mode" assembler directive. That will save us from adding
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* useless NOP_S padding in most of the cases.
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*
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* TODO: switch to ".bundle_align_mode" directive using whin it will be
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* supported by ARC toolchain.
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*/
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static __always_inline bool arch_static_branch(struct static_key *key,
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bool branch)
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{
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asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
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"1: \n"
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"nop \n"
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".pushsection __jump_table, \"aw\" \n"
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".word 1b, %l[l_yes], %c0 \n"
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".popsection \n"
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: : "i" (&((char *)key)[branch]) : : l_yes);
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return false;
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l_yes:
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return true;
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}
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static __always_inline bool arch_static_branch_jump(struct static_key *key,
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bool branch)
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{
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asm_volatile_goto(".balign "__stringify(JUMP_LABEL_NOP_SIZE)" \n"
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"1: \n"
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"b %l[l_yes] \n"
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".pushsection __jump_table, \"aw\" \n"
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".word 1b, %l[l_yes], %c0 \n"
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".popsection \n"
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: : "i" (&((char *)key)[branch]) : : l_yes);
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return false;
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l_yes:
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return true;
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}
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typedef u32 jump_label_t;
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struct jump_entry {
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jump_label_t code;
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jump_label_t target;
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jump_label_t key;
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};
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#endif /* __ASSEMBLY__ */
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#endif
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