// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Support for peripherals on the AXS10x mainboard (VDK version)
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*/
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/ {
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axs10x_mb_vdk {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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clocks {
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmcclk: mmcclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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pguclk: pguclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25175000>;
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};
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};
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ethernet@18000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = < 0x18000 0x2000 >;
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interrupts = < 4 >;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,phy-addr = < 0 >; // VDK model phy address is 0
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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};
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ehci@40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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interrupts = < 8 >;
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};
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uart@20000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20000 0x100>;
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clock-frequency = <2403200>;
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interrupts = <17>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@21000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x21000 0x100>;
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clock-frequency = <2403200>;
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interrupts = <18>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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clock-frequency = <2403200>;
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interrupts = <19>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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/* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
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pgu@17000 {
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compatible = "snps,arcpgu";
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reg = <0x17000 0x400>;
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clocks = <&pguclk>;
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clock-names = "pxlclk";
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};
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/* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
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ps2: ps2@e0017400 {
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compatible = "snps,arc_ps2";
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reg = <0x17400 0x14>;
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interrupts = <5>;
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interrupt-names = "arc_ps2_irq";
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};
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mmc@15000 {
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compatible = "snps,dw-mshc";
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reg = <0x15000 0x400>;
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fifo-depth = <1024>;
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card-detect-delay = <200>;
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clocks = <&apbclk>, <&mmcclk>;
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clock-names = "biu", "ciu";
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interrupts = <7>;
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bus-width = <4>;
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};
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};
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/*
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* Embedded Vision subsystem UIO mappings; only relevant for EV VDK
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*
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* This node is intentionally put outside of MB above becase
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* it maps areas outside of MB's 0xez-0xfz.
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*/
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uio_ev: uio@d0000000 {
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compatible = "generic-uio";
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reg = <0xd0000000 0x2000 0xd1000000 0x2000 0x90000000 0x10000000 0xc0000000 0x10000000>;
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reg-names = "ev_gsa", "ev_ctrl", "ev_shared_mem", "ev_code_mem";
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interrupt-parent = <&mb_intc>;
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interrupts = <23>;
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};
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};
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