/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __VPU_H__
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#define __VPU_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "rk_type.h"
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#define VPU_SUCCESS (0)
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#define VPU_FAILURE (-1)
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#define VPU_HW_WAIT_OK VPU_SUCCESS
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#define VPU_HW_WAIT_ERROR VPU_FAILURE
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#define VPU_HW_WAIT_TIMEOUT 1
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// vpu decoder 60 registers, size 240B
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#define VPU_REG_NUM_DEC (60)
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// vpu post processor 41 registers, size 164B
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#define VPU_REG_NUM_PP (41)
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// vpu decoder + post processor 101 registers, size 404B
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#define VPU_REG_NUM_DEC_PP (VPU_REG_NUM_DEC+VPU_REG_NUM_PP)
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// vpu encoder 96 registers, size 384B
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#define VPU_REG_NUM_ENC (96)
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typedef enum {
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VPU_ENC = 0x0,
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VPU_DEC = 0x1,
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VPU_PP = 0x2,
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VPU_DEC_PP = 0x3,
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VPU_DEC_HEVC = 0x4,
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VPU_DEC_RKV = 0x5,
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VPU_ENC_RKV = 0x6,
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VPU_DEC_AVS = 0x7,
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VPU_ENC_VEPU22 = 0x8,
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VPU_TYPE_BUTT ,
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} VPU_CLIENT_TYPE;
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/* Hardware decoder configuration description */
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typedef struct VPUHwDecConfig {
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RK_U32 maxDecPicWidth; /* Maximum video decoding width supported */
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RK_U32 maxPpOutPicWidth; /* Maximum output width of Post-Processor */
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RK_U32 h264Support; /* HW supports h.264 */
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RK_U32 jpegSupport; /* HW supports JPEG */
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RK_U32 mpeg4Support; /* HW supports MPEG-4 */
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RK_U32 customMpeg4Support; /* HW supports custom MPEG-4 features */
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RK_U32 vc1Support; /* HW supports VC-1 Simple */
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RK_U32 mpeg2Support; /* HW supports MPEG-2 */
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RK_U32 ppSupport; /* HW supports post-processor */
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RK_U32 ppConfig; /* HW post-processor functions bitmask */
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RK_U32 sorensonSparkSupport; /* HW supports Sorenson Spark */
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RK_U32 refBufSupport; /* HW supports reference picture buffering */
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RK_U32 vp6Support; /* HW supports VP6 */
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RK_U32 vp7Support; /* HW supports VP7 */
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RK_U32 vp8Support; /* HW supports VP8 */
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RK_U32 avsSupport; /* HW supports AVS */
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RK_U32 jpegESupport; /* HW supports JPEG extensions */
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RK_U32 rvSupport; /* HW supports REAL */
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RK_U32 mvcSupport; /* HW supports H264 MVC extension */
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} VPUHwDecConfig_t;
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/* Hardware encoder configuration description */
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typedef struct VPUHwEndConfig {
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RK_U32 maxEncodedWidth; /* Maximum supported width for video encoding (not JPEG) */
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RK_U32 h264Enabled; /* HW supports H.264 */
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RK_U32 jpegEnabled; /* HW supports JPEG */
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RK_U32 mpeg4Enabled; /* HW supports MPEG-4 */
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RK_U32 vsEnabled; /* HW supports video stabilization */
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RK_U32 rgbEnabled; /* HW supports RGB input */
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RK_U32 reg_size; /* HW bus type in use */
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RK_U32 reserv[2];
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} VPUHwEncConfig_t;
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typedef enum {
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// common command
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VPU_CMD_REGISTER ,
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VPU_CMD_REGISTER_ACK_OK ,
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VPU_CMD_REGISTER_ACK_FAIL ,
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VPU_CMD_UNREGISTER ,
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VPU_SEND_CONFIG ,
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VPU_SEND_CONFIG_ACK_OK ,
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VPU_SEND_CONFIG_ACK_FAIL ,
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VPU_GET_HW_INFO ,
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VPU_GET_HW_INFO_ACK_OK ,
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VPU_GET_HW_INFO_ACK_FAIL ,
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VPU_CMD_BUTT ,
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} VPU_CMD_TYPE;
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int VPUClientInit(VPU_CLIENT_TYPE type);
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RK_S32 VPUClientRelease(int socket);
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RK_S32 VPUClientSendReg(int socket, RK_U32 *regs, RK_U32 nregs);
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RK_S32 VPUClientSendReg2(RK_S32 socket, RK_S32 offset, RK_S32 size, void *param);
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RK_S32 VPUClientWaitResult(int socket, RK_U32 *regs, RK_U32 nregs, VPU_CMD_TYPE *cmd, RK_S32 *len);
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RK_S32 VPUClientGetHwCfg(int socket, RK_U32 *cfg, RK_U32 cfg_size);
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RK_S32 VPUClientGetIOMMUStatus();
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RK_U32 VPUCheckSupportWidth();
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#ifdef __cplusplus
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}
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#endif
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#endif /* __VPU_H__ */
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