/* Flags used to identify the presence of processor capabilities.
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Copyright (C) 2016 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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#ifndef GCC_ARM_FLAGS_H
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#define GCC_ARM_FLAGS_H
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/* Flags used to identify the presence of processor capabilities. */
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/* Bit values used to identify processor capabilities. */
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#define FL_NONE (0U) /* No flags. */
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#define FL_ANY (0xffffffffU) /* All flags. */
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#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */
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#define FL_ARCH3M (1U << 1) /* Extended multiply. */
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#define FL_MODE26 (1U << 2) /* 26-bit mode support. */
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#define FL_MODE32 (1U << 3) /* 32-bit mode support. */
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#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
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#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
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#define FL_THUMB (1U << 6) /* Thumb aware. */
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#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
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#define FL_STRONG (1U << 8) /* StrongARM. */
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#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
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#define FL_XSCALE (1U << 10) /* XScale. */
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/* spare (1U << 11) */
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#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
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media instructions. */
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#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
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#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
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Note: ARM6 & 7 derivatives only. */
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#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
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#define FL_THUMB2 (1U << 16) /* Thumb-2. */
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#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
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profile. */
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#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */
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#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */
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#define FL_NEON (1U << 20) /* Neon instructions. */
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#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M
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architecture. */
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#define FL_ARCH7 (1U << 22) /* Architecture 7. */
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#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
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#define FL_ARCH8 (1U << 24) /* Architecture 8. */
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#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
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#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
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#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
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#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
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technology". */
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#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2
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technology". */
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#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */
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#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */
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#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */
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#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and
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later. */
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#define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */
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/* Flags that only effect tuning, not available instructions. */
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#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
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| FL_CO_PROC)
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#define FL_FOR_ARCH2 FL_NOTM
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#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
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#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
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#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
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#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
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#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
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#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
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#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
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#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
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#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
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#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
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#define FL_FOR_ARCH6J FL_FOR_ARCH6
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#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
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#define FL_FOR_ARCH6Z FL_FOR_ARCH6
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#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
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#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
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#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
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#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
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#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
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#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
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#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
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#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
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#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
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#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
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#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
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#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
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#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
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#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
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#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8)
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/* There are too many feature bits to fit in a single word so the set of cpu and
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fpu capabilities is a structure. A feature set is created and manipulated
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with the ARM_FSET macros. */
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typedef struct
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{
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unsigned cpu[2];
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} arm_feature_set;
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/* Initialize a feature set. */
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#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
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#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
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#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
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/* Accessors. */
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#define ARM_FSET_CPU1(S) ((S).cpu[0])
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#define ARM_FSET_CPU2(S) ((S).cpu[1])
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/* Useful combinations. */
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#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
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#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
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/* Tests for a specific CPU feature. */
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#define ARM_FSET_HAS_CPU1(A, F) \
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(((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
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#define ARM_FSET_HAS_CPU2(A, F) \
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(((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
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#define ARM_FSET_HAS_CPU(A, F1, F2) \
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(ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
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/* Add a feature to a feature set. */
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#define ARM_FSET_ADD_CPU1(DST, F) \
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do { \
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(DST).cpu[0] |= (F); \
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} while (0)
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#define ARM_FSET_ADD_CPU2(DST, F) \
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do { \
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(DST).cpu[1] |= (F); \
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} while (0)
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/* Remove a feature from a feature set. */
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#define ARM_FSET_DEL_CPU1(DST, F) \
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do { \
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(DST).cpu[0] &= ~(F); \
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} while (0)
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#define ARM_FSET_DEL_CPU2(DST, F) \
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do { \
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(DST).cpu[1] &= ~(F); \
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} while (0)
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/* Union of feature sets. */
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#define ARM_FSET_UNION(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
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} while (0)
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/* Intersection of feature sets. */
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#define ARM_FSET_INTER(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
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} while (0)
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/* Exclusive disjunction. */
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#define ARM_FSET_XOR(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
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} while (0)
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/* Difference of feature sets: F1 excluding the elements of F2. */
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#define ARM_FSET_EXCLUDE(DST,F1,F2) \
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do { \
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(DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
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(DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
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} while (0)
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/* Test for an empty feature set. */
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#define ARM_FSET_IS_EMPTY(A) \
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(!((A).cpu[0]) && !((A).cpu[1]))
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/* Tests whether the cpu features of A are a subset of B. */
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#define ARM_FSET_CPU_SUBSET(A,B) \
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((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
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&& (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
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#endif /* GCC_ARM_FLAGS_H */
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