/* Copyright (C) 2015-2020 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published
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by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* Additional control over certain tuning parameters. Before including
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this file, define a macro:
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AARCH64_EXTRA_TUNING_OPTION (name, internal_name)
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Where:
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NAME is a string giving a friendly name for the tuning flag.
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INTERNAL_NAME gives the internal name suitable for appending to
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AARCH64_TUNE_ to give an enum name. */
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AARCH64_EXTRA_TUNING_OPTION ("rename_fma_regs", RENAME_FMA_REGS)
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/* Don't create non-8 byte aligned load/store pair. That is if the
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two load/stores are not at least 8 byte aligned don't create load/store
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pairs. */
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AARCH64_EXTRA_TUNING_OPTION ("slow_unaligned_ldpw", SLOW_UNALIGNED_LDPW)
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/* Some of the optional shift to some arthematic instructions are
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considered cheap. Logical shift left <=4 with or without a
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zero extend are considered cheap. Sign extend; non logical shift left
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are not considered cheap. */
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AARCH64_EXTRA_TUNING_OPTION ("cheap_shift_extend", CHEAP_SHIFT_EXTEND)
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/* Disallow load/store pair instructions on Q-registers. */
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AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", NO_LDP_STP_QREGS)
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AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", RENAME_LOAD_REGS)
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/* Prefer Advanced SIMD over SVE for auto-vectorization. */
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AARCH64_EXTRA_TUNING_OPTION ("prefer_advsimd_autovec", PREFER_ADVSIMD_AUTOVEC)
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AARCH64_EXTRA_TUNING_OPTION ("cse_sve_vl_constants", CSE_SVE_VL_CONSTANTS)
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#undef AARCH64_EXTRA_TUNING_OPTION
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