/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "../i915_selftest.h"
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static int intel_fw_table_check(const struct intel_forcewake_range *ranges,
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unsigned int num_ranges,
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bool is_watertight)
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{
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unsigned int i;
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s32 prev;
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for (i = 0, prev = -1; i < num_ranges; i++, ranges++) {
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/* Check that the table is watertight */
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if (is_watertight && (prev + 1) != (s32)ranges->start) {
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pr_err("%s: entry[%d]:(%x, %x) is not watertight to previous (%x)\n",
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__func__, i, ranges->start, ranges->end, prev);
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return -EINVAL;
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}
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/* Check that the table never goes backwards */
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if (prev >= (s32)ranges->start) {
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pr_err("%s: entry[%d]:(%x, %x) is less than the previous (%x)\n",
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__func__, i, ranges->start, ranges->end, prev);
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return -EINVAL;
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}
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/* Check that the entry is valid */
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if (ranges->start >= ranges->end) {
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pr_err("%s: entry[%d]:(%x, %x) has negative length\n",
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__func__, i, ranges->start, ranges->end);
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return -EINVAL;
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}
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prev = ranges->end;
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}
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return 0;
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}
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static int intel_shadow_table_check(void)
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{
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struct {
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const i915_reg_t *regs;
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unsigned int size;
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} reg_lists[] = {
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{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
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{ gen11_shadowed_regs, ARRAY_SIZE(gen11_shadowed_regs) },
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};
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const i915_reg_t *reg;
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unsigned int i, j;
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s32 prev;
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for (j = 0; j < ARRAY_SIZE(reg_lists); ++j) {
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reg = reg_lists[j].regs;
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for (i = 0, prev = -1; i < reg_lists[j].size; i++, reg++) {
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u32 offset = i915_mmio_reg_offset(*reg);
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if (prev >= (s32)offset) {
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pr_err("%s: entry[%d]:(%x) is before previous (%x)\n",
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__func__, i, offset, prev);
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return -EINVAL;
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}
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prev = offset;
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}
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}
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return 0;
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}
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int intel_uncore_mock_selftests(void)
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{
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struct {
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const struct intel_forcewake_range *ranges;
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unsigned int num_ranges;
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bool is_watertight;
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} fw[] = {
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{ __vlv_fw_ranges, ARRAY_SIZE(__vlv_fw_ranges), false },
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{ __chv_fw_ranges, ARRAY_SIZE(__chv_fw_ranges), false },
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{ __gen9_fw_ranges, ARRAY_SIZE(__gen9_fw_ranges), true },
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{ __gen11_fw_ranges, ARRAY_SIZE(__gen11_fw_ranges), true },
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};
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int err, i;
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for (i = 0; i < ARRAY_SIZE(fw); i++) {
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err = intel_fw_table_check(fw[i].ranges,
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fw[i].num_ranges,
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fw[i].is_watertight);
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if (err)
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return err;
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}
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err = intel_shadow_table_check();
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if (err)
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return err;
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return 0;
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}
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static int intel_uncore_check_forcewake_domains(struct drm_i915_private *dev_priv)
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{
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#define FW_RANGE 0x40000
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unsigned long *valid;
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u32 offset;
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int err;
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if (!HAS_FPGA_DBG_UNCLAIMED(dev_priv) &&
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!IS_VALLEYVIEW(dev_priv) &&
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!IS_CHERRYVIEW(dev_priv))
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return 0;
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/*
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* This test may lockup the machine or cause GPU hangs afterwards.
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*/
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if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
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return 0;
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valid = kcalloc(BITS_TO_LONGS(FW_RANGE), sizeof(*valid),
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GFP_KERNEL);
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if (!valid)
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return -ENOMEM;
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intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
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check_for_unclaimed_mmio(dev_priv);
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for (offset = 0; offset < FW_RANGE; offset += 4) {
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i915_reg_t reg = { offset };
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(void)I915_READ_FW(reg);
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if (!check_for_unclaimed_mmio(dev_priv))
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set_bit(offset, valid);
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}
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intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
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err = 0;
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for_each_set_bit(offset, valid, FW_RANGE) {
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i915_reg_t reg = { offset };
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iosf_mbi_punit_acquire();
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intel_uncore_forcewake_reset(dev_priv);
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iosf_mbi_punit_release();
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check_for_unclaimed_mmio(dev_priv);
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(void)I915_READ(reg);
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if (check_for_unclaimed_mmio(dev_priv)) {
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pr_err("Unclaimed mmio read to register 0x%04x\n",
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offset);
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err = -EINVAL;
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}
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}
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kfree(valid);
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return err;
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}
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int intel_uncore_live_selftests(struct drm_i915_private *i915)
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{
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int err;
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/* Confirm the table we load is still valid */
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err = intel_fw_table_check(i915->uncore.fw_domains_table,
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i915->uncore.fw_domains_table_entries,
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INTEL_GEN(i915) >= 9);
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if (err)
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return err;
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err = intel_uncore_check_forcewake_domains(i915);
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if (err)
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return err;
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return 0;
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}
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