/*
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* Copyright © 2018 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Madhav Chauhan <madhav.chauhan@intel.com>
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* Jani Nikula <jani.nikula@intel.com>
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*/
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#include "intel_dsi.h"
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static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
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u32 afe_clk_khz; /* 8X Clock */
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u32 esc_clk_div_m;
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afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
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intel_dsi->lane_count);
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esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
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for_each_dsi_port(port, intel_dsi->ports) {
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I915_WRITE(ICL_DSI_ESC_CLK_DIV(port),
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esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
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POSTING_READ(ICL_DSI_ESC_CLK_DIV(port));
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}
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for_each_dsi_port(port, intel_dsi->ports) {
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I915_WRITE(ICL_DPHY_ESC_CLK_DIV(port),
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esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
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POSTING_READ(ICL_DPHY_ESC_CLK_DIV(port));
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}
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}
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static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 tmp;
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = I915_READ(ICL_DSI_IO_MODECTL(port));
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tmp |= COMBO_PHY_MODE_DSI;
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I915_WRITE(ICL_DSI_IO_MODECTL(port), tmp);
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}
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for_each_dsi_port(port, intel_dsi->ports) {
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intel_display_power_get(dev_priv, port == PORT_A ?
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POWER_DOMAIN_PORT_DDI_A_IO :
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POWER_DOMAIN_PORT_DDI_B_IO);
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}
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}
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static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
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enum port port;
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u32 tmp;
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u32 lane_mask;
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switch (intel_dsi->lane_count) {
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case 1:
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lane_mask = PWR_DOWN_LN_3_1_0;
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break;
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case 2:
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lane_mask = PWR_DOWN_LN_3_1;
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break;
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case 3:
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lane_mask = PWR_DOWN_LN_3;
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break;
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case 4:
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default:
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lane_mask = PWR_UP_ALL_LANES;
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break;
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}
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for_each_dsi_port(port, intel_dsi->ports) {
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tmp = I915_READ(ICL_PORT_CL_DW10(port));
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tmp &= ~PWR_DOWN_LN_MASK;
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I915_WRITE(ICL_PORT_CL_DW10(port), tmp | lane_mask);
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}
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}
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static void gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder)
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{
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/* step 4a: power up all lanes of the DDI used by DSI */
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gen11_dsi_power_up_lanes(encoder);
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}
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static void __attribute__((unused))
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gen11_dsi_pre_enable(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config,
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const struct drm_connector_state *conn_state)
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{
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/* step2: enable IO power */
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gen11_dsi_enable_io_power(encoder);
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/* step3: enable DSI PLL */
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gen11_dsi_program_esc_clk_div(encoder);
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/* step4: enable DSI port and DPHY */
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gen11_dsi_enable_port_and_phy(encoder);
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}
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