1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
| /*
| * R-Car Gen3 Clock Pulse Generator
| *
| * Copyright (C) 2015-2016 Glider bvba
| *
| * This program is free software; you can redistribute it and/or modify
| * it under the terms of the GNU General Public License as published by
| * the Free Software Foundation; version 2 of the License.
| */
|
| #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
| #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
| enum rcar_gen3_clk_types {
| CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
| CLK_TYPE_GEN3_PLL0,
| CLK_TYPE_GEN3_PLL1,
| CLK_TYPE_GEN3_PLL2,
| CLK_TYPE_GEN3_PLL3,
| CLK_TYPE_GEN3_PLL4,
| CLK_TYPE_GEN3_SD,
| CLK_TYPE_GEN3_R,
| CLK_TYPE_GEN3_PE,
| CLK_TYPE_GEN3_Z,
| CLK_TYPE_GEN3_Z2,
| };
|
| #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
| DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
| #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
| _div_clean) \
| DEF_BASE(_name, _id, CLK_TYPE_GEN3_PE, \
| (_parent_sscg) << 16 | (_parent_clean), \
| .div = (_div_sscg) << 16 | (_div_clean))
|
| struct rcar_gen3_cpg_pll_config {
| u8 extal_div;
| u8 pll1_mult;
| u8 pll1_div;
| u8 pll3_mult;
| u8 pll3_div;
| };
|
| #define CPG_RCKCR 0x240
|
| struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
| const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
| struct clk **clks, void __iomem *base,
| struct raw_notifier_head *notifiers);
| int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
| unsigned int clk_extalr, u32 mode);
|
| #endif
|
|
