// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*
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* author:
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* Ding Wei, leo.ding@rock-chips.com
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* Alpha Lin, alpha.lin@rock-chips.com
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*
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*/
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#include <asm/cacheflush.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <linux/dma-buf.h>
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#include <linux/uaccess.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <linux/proc_fs.h>
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#include <linux/mfd/syscon.h>
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#include <linux/rockchip/cpu.h>
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#include <soc/rockchip/pm_domains.h>
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#include "rockchip_iep2_regs.h"
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#include "mpp_debug.h"
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#include "mpp_common.h"
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#include "mpp_iommu.h"
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#define IEP2_DRIVER_NAME "mpp-iep2"
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#define IEP2_SESSION_MAX_BUFFERS 20
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#define TILE_WIDTH 16
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#define TILE_HEIGHT 4
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#define MVL 28
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#define MVR 27
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enum rockchip_iep2_fmt {
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ROCKCHIP_IEP2_FMT_YUV422 = 2,
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ROCKCHIP_IEP2_FMT_YUV420
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};
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enum rockchip_iep2_yuv_swap {
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ROCKCHIP_IEP2_YUV_SWAP_SP_UV,
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ROCKCHIP_IEP2_YUV_SWAP_SP_VU,
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ROCKCHIP_IEP2_YUV_SWAP_P0,
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ROCKCHIP_IEP2_YUV_SWAP_P
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};
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enum rockchip_iep2_dil_ff_order {
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ROCKCHIP_IEP2_DIL_FF_ORDER_TB,
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ROCKCHIP_IEP2_DIL_FF_ORDER_BT
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};
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enum rockchip_iep2_dil_mode {
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ROCKCHIP_IEP2_DIL_MODE_DISABLE,
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ROCKCHIP_IEP2_DIL_MODE_I5O2,
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ROCKCHIP_IEP2_DIL_MODE_I5O1T,
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ROCKCHIP_IEP2_DIL_MODE_I5O1B,
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ROCKCHIP_IEP2_DIL_MODE_I2O2,
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ROCKCHIP_IEP2_DIL_MODE_I1O1T,
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ROCKCHIP_IEP2_DIL_MODE_I1O1B,
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ROCKCHIP_IEP2_DIL_MODE_PD,
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ROCKCHIP_IEP2_DIL_MODE_BYPASS,
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ROCKCHIP_IEP2_DIL_MODE_DECT
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};
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enum ROCKCHIP_IEP2_PD_COMP_FLAG {
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ROCKCHIP_IEP2_PD_COMP_FLAG_CC,
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ROCKCHIP_IEP2_PD_COMP_FLAG_CN,
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ROCKCHIP_IEP2_PD_COMP_FLAG_NC,
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ROCKCHIP_IEP2_PD_COMP_FLAG_NON
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};
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/* default iep2 mtn table */
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static u32 iep2_mtn_tab[] = {
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0x00000000, 0x00000000, 0x00000000, 0x00000000,
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0x01010000, 0x06050302, 0x0f0d0a08, 0x1c191512,
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0x2b282420, 0x3634312e, 0x3d3c3a38, 0x40403f3e,
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0x40404040, 0x40404040, 0x40404040, 0x40404040
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};
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#define to_iep_task(task) \
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container_of(task, struct iep_task, mpp_task)
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#define to_iep2_dev(dev) \
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container_of(dev, struct iep2_dev, mpp)
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struct iep2_addr {
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u32 y;
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u32 cbcr;
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u32 cr;
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};
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struct iep2_params {
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u32 src_fmt;
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u32 src_yuv_swap;
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u32 dst_fmt;
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u32 dst_yuv_swap;
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u32 tile_cols;
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u32 tile_rows;
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u32 src_y_stride;
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u32 src_uv_stride;
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u32 dst_y_stride;
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/* current, previous, next. */
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struct iep2_addr src[3];
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struct iep2_addr dst[2];
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u32 mv_addr;
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u32 md_addr;
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u32 dil_mode;
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u32 dil_out_mode;
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u32 dil_field_order;
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u32 md_theta;
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u32 md_r;
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u32 md_lambda;
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u32 dect_resi_thr;
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u32 osd_area_num;
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u32 osd_gradh_thr;
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u32 osd_gradv_thr;
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u32 osd_pos_limit_en;
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u32 osd_pos_limit_num;
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u32 osd_limit_area[2];
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u32 osd_line_num;
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u32 osd_pec_thr;
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u32 osd_x_sta[8];
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u32 osd_x_end[8];
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u32 osd_y_sta[8];
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u32 osd_y_end[8];
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u32 me_pena;
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u32 mv_bonus;
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u32 mv_similar_thr;
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u32 mv_similar_num_thr0;
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s32 me_thr_offset;
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u32 mv_left_limit;
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u32 mv_right_limit;
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s8 mv_tru_list[8];
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u32 mv_tru_vld[8];
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u32 eedi_thr0;
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u32 ble_backtoma_num;
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u32 comb_cnt_thr;
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u32 comb_feature_thr;
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u32 comb_t_thr;
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u32 comb_osd_vld[8];
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u32 mtn_en;
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u32 mtn_tab[16];
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u32 pd_mode;
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u32 roi_en;
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u32 roi_layer_num;
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u32 roi_mode[8];
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u32 xsta[8];
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u32 xend[8];
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u32 ysta[8];
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u32 yend[8];
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};
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struct iep2_output {
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u32 mv_hist[MVL + MVR + 1];
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u32 dect_pd_tcnt;
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u32 dect_pd_bcnt;
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u32 dect_ff_cur_tcnt;
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u32 dect_ff_cur_bcnt;
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u32 dect_ff_nxt_tcnt;
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u32 dect_ff_nxt_bcnt;
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u32 dect_ff_ble_tcnt;
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u32 dect_ff_ble_bcnt;
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u32 dect_ff_nz;
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u32 dect_ff_comb_f;
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u32 dect_osd_cnt;
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u32 out_comb_cnt;
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u32 out_osd_comb_cnt;
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u32 ff_gradt_tcnt;
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u32 ff_gradt_bcnt;
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u32 x_sta[8];
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u32 x_end[8];
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u32 y_sta[8];
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u32 y_end[8];
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};
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struct iep_task {
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struct mpp_task mpp_task;
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struct mpp_hw_info *hw_info;
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enum MPP_CLOCK_MODE clk_mode;
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struct iep2_params params;
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struct iep2_output output;
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struct reg_offset_info off_inf;
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u32 irq_status;
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/* req for current task */
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u32 w_req_cnt;
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struct mpp_request w_reqs[MPP_MAX_MSG_NUM];
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u32 r_req_cnt;
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struct mpp_request r_reqs[MPP_MAX_MSG_NUM];
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};
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struct iep2_dev {
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struct mpp_dev mpp;
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struct mpp_clk_info aclk_info;
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struct mpp_clk_info hclk_info;
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struct mpp_clk_info sclk_info;
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#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
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struct proc_dir_entry *procfs;
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#endif
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struct reset_control *rst_a;
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struct reset_control *rst_h;
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struct reset_control *rst_s;
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struct mpp_dma_buffer roi;
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};
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static int iep2_addr_rnum[] = {
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24, 27, 28, /* src cur */
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25, 29, 30, /* src nxt */
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26, 31, 32, /* src prv */
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44, 46, -1, /* dst top */
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45, 47, -1, /* dst bot */
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34, /* mv */
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33, /* md */
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};
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static int iep2_process_reg_fd(struct mpp_session *session,
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struct iep_task *task,
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struct mpp_task_msgs *msgs)
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{
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int i;
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/* see the detail at above table iep2_addr_rnum */
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int addr_num =
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ARRAY_SIZE(task->params.src) * 3 +
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ARRAY_SIZE(task->params.dst) * 3 + 2;
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u32 *paddr = &task->params.src[0].y;
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for (i = 0; i < addr_num; ++i) {
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int usr_fd;
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u32 offset;
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struct mpp_mem_region *mem_region = NULL;
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if (session->msg_flags & MPP_FLAGS_REG_NO_OFFSET) {
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usr_fd = paddr[i];
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offset = 0;
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} else {
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usr_fd = paddr[i] & 0x3ff;
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offset = paddr[i] >> 10;
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}
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if (usr_fd == 0 || iep2_addr_rnum[i] == -1)
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continue;
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mem_region = mpp_task_attach_fd(&task->mpp_task, usr_fd);
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if (IS_ERR(mem_region)) {
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mpp_debug(DEBUG_IOMMU, "reg[%3d]: %08x failed\n",
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iep2_addr_rnum[i], paddr[i]);
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return PTR_ERR(mem_region);
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}
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mem_region->reg_idx = iep2_addr_rnum[i];
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mpp_debug(DEBUG_IOMMU, "reg[%3d]: %3d => %pad + offset %10d\n",
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iep2_addr_rnum[i], usr_fd, &mem_region->iova, offset);
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paddr[i] = mem_region->iova + offset;
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}
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return 0;
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}
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static int iep2_extract_task_msg(struct iep_task *task,
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struct mpp_task_msgs *msgs)
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{
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u32 i;
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struct mpp_request *req;
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for (i = 0; i < msgs->req_cnt; i++) {
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req = &msgs->reqs[i];
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if (!req->size)
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continue;
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switch (req->cmd) {
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case MPP_CMD_SET_REG_WRITE: {
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if (copy_from_user(&task->params,
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req->data, req->size)) {
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mpp_err("copy_from_user params failed\n");
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return -EIO;
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}
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} break;
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case MPP_CMD_SET_REG_READ: {
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memcpy(&task->r_reqs[task->r_req_cnt++],
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req, sizeof(*req));
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} break;
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case MPP_CMD_SET_REG_ADDR_OFFSET: {
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mpp_extract_reg_offset_info(&task->off_inf, req);
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} break;
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default:
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break;
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}
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}
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mpp_debug(DEBUG_TASK_INFO, "w_req_cnt %d, r_req_cnt %d\n",
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task->w_req_cnt, task->r_req_cnt);
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return 0;
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}
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static void *iep2_alloc_task(struct mpp_session *session,
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struct mpp_task_msgs *msgs)
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{
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int ret;
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struct iep_task *task = NULL;
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mpp_debug_enter();
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task = kzalloc(sizeof(*task), GFP_KERNEL);
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if (!task)
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return NULL;
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mpp_task_init(session, &task->mpp_task);
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/* extract reqs for current task */
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ret = iep2_extract_task_msg(task, msgs);
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if (ret)
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goto fail;
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/* process fd in register */
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if (!(msgs->flags & MPP_FLAGS_REG_FD_NO_TRANS)) {
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ret = iep2_process_reg_fd(session, task, msgs);
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if (ret)
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goto fail;
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}
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task->clk_mode = CLK_MODE_NORMAL;
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mpp_debug_leave();
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return &task->mpp_task;
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fail:
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mpp_task_finalize(session, &task->mpp_task);
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kfree(task);
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return NULL;
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}
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static void iep2_config(struct mpp_dev *mpp, struct iep_task *task)
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{
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struct iep2_dev *iep = to_iep2_dev(mpp);
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struct iep2_params *cfg = &task->params;
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u32 reg;
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u32 width, height;
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width = cfg->tile_cols * TILE_WIDTH;
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height = cfg->tile_rows * TILE_HEIGHT;
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reg = IEP2_REG_SRC_FMT(cfg->src_fmt)
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| IEP2_REG_SRC_YUV_SWAP(cfg->src_yuv_swap)
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| IEP2_REG_DST_FMT(cfg->dst_fmt)
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| IEP2_REG_DST_YUV_SWAP(cfg->dst_yuv_swap)
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| IEP2_REG_DEBUG_DATA_EN;
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mpp_write_relaxed(mpp, IEP2_REG_IEP_CONFIG0, reg);
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mpp_write_relaxed(mpp, IEP2_REG_WORK_MODE, IEP2_REG_IEP2_MODE);
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reg = IEP2_REG_SRC_PIC_WIDTH(width - 1)
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| IEP2_REG_SRC_PIC_HEIGHT(height - 1);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_IMG_SIZE, reg);
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reg = IEP2_REG_SRC_VIR_Y_STRIDE(cfg->src_y_stride)
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| IEP2_REG_SRC_VIR_UV_STRIDE(cfg->src_uv_stride);
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mpp_write_relaxed(mpp, IEP2_REG_VIR_SRC_IMG_WIDTH, reg);
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reg = IEP2_REG_DST_VIR_STRIDE(cfg->dst_y_stride);
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mpp_write_relaxed(mpp, IEP2_REG_VIR_DST_IMG_WIDTH, reg);
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reg = IEP2_REG_DIL_MV_HIST_EN
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| IEP2_REG_DIL_COMB_EN
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| IEP2_REG_DIL_BLE_EN
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| IEP2_REG_DIL_EEDI_EN
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| IEP2_REG_DIL_MEMC_EN
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| IEP2_REG_DIL_OSD_EN
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| IEP2_REG_DIL_PD_EN
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| IEP2_REG_DIL_FF_EN
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| IEP2_REG_DIL_FIELD_ORDER(cfg->dil_field_order)
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| IEP2_REG_DIL_OUT_MODE(cfg->dil_out_mode)
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| IEP2_REG_DIL_MODE(cfg->dil_mode);
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if (cfg->roi_en)
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reg |= IEP2_REG_DIL_ROI_EN;
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if (cfg->md_lambda < 8)
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reg |= IEP2_REG_DIL_MD_PRE_EN;
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mpp_write_relaxed(mpp, IEP2_REG_DIL_CONFIG0, reg);
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if (cfg->dil_mode != ROCKCHIP_IEP2_DIL_MODE_PD) {
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURY,
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cfg->src[0].y);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURUV,
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cfg->src[0].cbcr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURV,
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cfg->src[0].cr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTY,
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cfg->src[1].y);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTUV,
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cfg->src[1].cbcr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTV,
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cfg->src[1].cr);
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} else {
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struct iep2_addr *top, *bot;
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switch (cfg->pd_mode) {
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default:
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case ROCKCHIP_IEP2_PD_COMP_FLAG_CC:
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top = &cfg->src[0];
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bot = &cfg->src[0];
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break;
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case ROCKCHIP_IEP2_PD_COMP_FLAG_CN:
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top = &cfg->src[0];
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bot = &cfg->src[1];
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break;
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case ROCKCHIP_IEP2_PD_COMP_FLAG_NC:
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top = &cfg->src[1];
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bot = &cfg->src[0];
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break;
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}
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURY, top->y);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURUV, top->cbcr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_CURV, top->cr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTY, bot->y);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTUV, bot->cbcr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_NXTV, bot->cr);
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}
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reg = IEP2_REG_TIMEOUT_CFG_EN | 0x3ffffff;
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mpp_write_relaxed(mpp, IEP2_REG_TIMEOUT_CFG, reg);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_PREY, cfg->src[2].y);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_PREUV, cfg->src[2].cbcr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_PREV, cfg->src[2].cr);
|
|
mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_MD, cfg->md_addr);
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mpp_write_relaxed(mpp, IEP2_REG_SRC_ADDR_MV, cfg->mv_addr);
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_MD, cfg->md_addr);
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_MV, cfg->mv_addr);
|
mpp_write_relaxed(mpp, IEP2_REG_ROI_ADDR, (u32)iep->roi.iova);
|
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_TOPY, cfg->dst[0].y);
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_TOPC, cfg->dst[0].cbcr);
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_BOTY, cfg->dst[1].y);
|
mpp_write_relaxed(mpp, IEP2_REG_DST_ADDR_BOTC, cfg->dst[1].cbcr);
|
|
reg = IEP2_REG_MD_THETA(cfg->md_theta)
|
| IEP2_REG_MD_R(cfg->md_r)
|
| IEP2_REG_MD_LAMBDA(cfg->md_lambda);
|
mpp_write_relaxed(mpp, IEP2_REG_MD_CONFIG0, reg);
|
|
reg = IEP2_REG_DECT_RESI_THR(cfg->dect_resi_thr)
|
| IEP2_REG_OSD_AREA_NUM(cfg->osd_area_num)
|
| IEP2_REG_OSD_GRADH_THR(cfg->osd_gradh_thr)
|
| IEP2_REG_OSD_GRADV_THR(cfg->osd_gradv_thr);
|
mpp_write_relaxed(mpp, IEP2_REG_DECT_CONFIG0, reg);
|
|
reg = IEP2_REG_OSD_POS_LIMIT_NUM(cfg->osd_pos_limit_num);
|
if (cfg->osd_pos_limit_en)
|
reg |= IEP2_REG_OSD_POS_LIMIT_EN;
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_LIMIT_CONFIG, reg);
|
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_LIMIT_AREA(0),
|
cfg->osd_limit_area[0]);
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_LIMIT_AREA(1),
|
cfg->osd_limit_area[1]);
|
|
reg = IEP2_REG_OSD_PEC_THR(cfg->osd_pec_thr)
|
| IEP2_REG_OSD_LINE_NUM(cfg->osd_line_num);
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_CONFIG0, reg);
|
|
reg = IEP2_REG_ME_PENA(cfg->me_pena)
|
| IEP2_REG_MV_BONUS(cfg->mv_bonus)
|
| IEP2_REG_MV_SIMILAR_THR(cfg->mv_similar_thr)
|
| IEP2_REG_MV_SIMILAR_NUM_THR0(cfg->mv_similar_num_thr0)
|
| IEP2_REG_ME_THR_OFFSET(cfg->me_thr_offset);
|
mpp_write_relaxed(mpp, IEP2_REG_ME_CONFIG0, reg);
|
|
reg = IEP2_REG_MV_LEFT_LIMIT((~cfg->mv_left_limit) + 1)
|
| IEP2_REG_MV_RIGHT_LIMIT(cfg->mv_right_limit);
|
mpp_write_relaxed(mpp, IEP2_REG_ME_LIMIT_CONFIG, reg);
|
|
mpp_write_relaxed(mpp, IEP2_REG_EEDI_CONFIG0,
|
IEP2_REG_EEDI_THR0(cfg->eedi_thr0));
|
mpp_write_relaxed(mpp, IEP2_REG_BLE_CONFIG0,
|
IEP2_REG_BLE_BACKTOMA_NUM(cfg->ble_backtoma_num));
|
}
|
|
static void iep2_osd_cfg(struct mpp_dev *mpp, struct iep_task *task)
|
{
|
struct iep2_params *hw_cfg = &task->params;
|
int i;
|
u32 reg;
|
|
for (i = 0; i < hw_cfg->osd_area_num; ++i) {
|
reg = IEP2_REG_OSD_X_STA(hw_cfg->osd_x_sta[i])
|
| IEP2_REG_OSD_X_END(hw_cfg->osd_x_end[i])
|
| IEP2_REG_OSD_Y_STA(hw_cfg->osd_y_sta[i])
|
| IEP2_REG_OSD_Y_END(hw_cfg->osd_y_end[i]);
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_AREA_CONF(i), reg);
|
}
|
|
for (; i < ARRAY_SIZE(hw_cfg->osd_x_sta); ++i)
|
mpp_write_relaxed(mpp, IEP2_REG_OSD_AREA_CONF(i), 0);
|
}
|
|
static void iep2_mtn_tab_cfg(struct mpp_dev *mpp, struct iep_task *task)
|
{
|
struct iep2_params *hw_cfg = &task->params;
|
int i;
|
u32 *mtn_tab = hw_cfg->mtn_en ? hw_cfg->mtn_tab : iep2_mtn_tab;
|
|
for (i = 0; i < ARRAY_SIZE(hw_cfg->mtn_tab); ++i)
|
mpp_write_relaxed(mpp, IEP2_REG_DIL_MTN_TAB(i), mtn_tab[i]);
|
}
|
|
static u32 iep2_tru_list_vld_tab[] = {
|
IEP2_REG_MV_TRU_LIST0_4_VLD, IEP2_REG_MV_TRU_LIST1_5_VLD,
|
IEP2_REG_MV_TRU_LIST2_6_VLD, IEP2_REG_MV_TRU_LIST3_7_VLD,
|
IEP2_REG_MV_TRU_LIST0_4_VLD, IEP2_REG_MV_TRU_LIST1_5_VLD,
|
IEP2_REG_MV_TRU_LIST2_6_VLD, IEP2_REG_MV_TRU_LIST3_7_VLD
|
};
|
|
static void iep2_tru_list_cfg(struct mpp_dev *mpp, struct iep_task *task)
|
{
|
struct iep2_params *cfg = &task->params;
|
int i;
|
u32 reg;
|
|
for (i = 0; i < ARRAY_SIZE(cfg->mv_tru_list); i += 4) {
|
reg = 0;
|
|
if (cfg->mv_tru_vld[i])
|
reg |= IEP2_REG_MV_TRU_LIST0_4(cfg->mv_tru_list[i])
|
| iep2_tru_list_vld_tab[i];
|
|
if (cfg->mv_tru_vld[i + 1])
|
reg |= IEP2_REG_MV_TRU_LIST1_5(cfg->mv_tru_list[i + 1])
|
| iep2_tru_list_vld_tab[i + 1];
|
|
if (cfg->mv_tru_vld[i + 2])
|
reg |= IEP2_REG_MV_TRU_LIST2_6(cfg->mv_tru_list[i + 2])
|
| iep2_tru_list_vld_tab[i + 2];
|
|
if (cfg->mv_tru_vld[i + 3])
|
reg |= IEP2_REG_MV_TRU_LIST3_7(cfg->mv_tru_list[i + 3])
|
| iep2_tru_list_vld_tab[i + 3];
|
|
mpp_write_relaxed(mpp, IEP2_REG_MV_TRU_LIST(i / 4), reg);
|
}
|
}
|
|
static void iep2_comb_cfg(struct mpp_dev *mpp, struct iep_task *task)
|
{
|
struct iep2_params *hw_cfg = &task->params;
|
int i;
|
u32 reg = 0;
|
|
for (i = 0; i < ARRAY_SIZE(hw_cfg->comb_osd_vld); ++i) {
|
if (hw_cfg->comb_osd_vld[i])
|
reg |= IEP2_REG_COMB_OSD_VLD(i);
|
}
|
|
reg |= IEP2_REG_COMB_T_THR(hw_cfg->comb_t_thr)
|
| IEP2_REG_COMB_FEATRUE_THR(hw_cfg->comb_feature_thr)
|
| IEP2_REG_COMB_CNT_THR(hw_cfg->comb_cnt_thr);
|
mpp_write_relaxed(mpp, IEP2_REG_COMB_CONFIG0, reg);
|
}
|
|
static int iep2_run(struct mpp_dev *mpp,
|
struct mpp_task *mpp_task)
|
{
|
struct iep_task *task = NULL;
|
u32 timing_en = mpp->srv->timing_en;
|
|
mpp_debug_enter();
|
|
task = to_iep_task(mpp_task);
|
|
/* init current task */
|
mpp->cur_task = mpp_task;
|
|
iep2_config(mpp, task);
|
iep2_osd_cfg(mpp, task);
|
iep2_mtn_tab_cfg(mpp, task);
|
iep2_tru_list_cfg(mpp, task);
|
iep2_comb_cfg(mpp, task);
|
|
/* set interrupt enable bits */
|
mpp_write_relaxed(mpp, IEP2_REG_INT_EN,
|
IEP2_REG_FRM_DONE_EN
|
| IEP2_REG_OSD_MAX_EN
|
| IEP2_REG_BUS_ERROR_EN
|
| IEP2_REG_TIMEOUT_EN);
|
|
/* flush tlb before starting hardware */
|
mpp_iommu_flush_tlb(mpp->iommu_info);
|
|
mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
|
|
/* Last, flush the registers */
|
wmb();
|
/* start iep2 */
|
mpp_write(mpp, IEP2_REG_FRM_START, 1);
|
|
mpp_task_run_end(mpp_task, timing_en);
|
|
mpp_debug_leave();
|
|
return 0;
|
}
|
|
static int iep2_irq(struct mpp_dev *mpp)
|
{
|
u32 work_mode = mpp_read(mpp, IEP2_REG_WORK_MODE);
|
|
if (work_mode && !(work_mode & IEP2_REG_IEP2_MODE))
|
return IRQ_NONE;
|
mpp->irq_status = mpp_read(mpp, IEP2_REG_INT_STS);
|
mpp_write(mpp, IEP2_REG_INT_CLR, 0xffffffff);
|
|
if (!IEP2_REG_RO_VALID_INT_STS(mpp->irq_status))
|
return IRQ_NONE;
|
|
return IRQ_WAKE_THREAD;
|
}
|
|
static int iep2_isr(struct mpp_dev *mpp)
|
{
|
struct mpp_task *mpp_task = NULL;
|
struct iep_task *task = NULL;
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
mpp_task = mpp->cur_task;
|
task = to_iep_task(mpp_task);
|
if (!task) {
|
dev_err(iep->mpp.dev, "no current task\n");
|
return IRQ_HANDLED;
|
}
|
|
mpp_time_diff(mpp_task);
|
mpp->cur_task = NULL;
|
task->irq_status = mpp->irq_status;
|
mpp_debug(DEBUG_IRQ_STATUS, "irq_status: %08x\n",
|
task->irq_status);
|
|
if (IEP2_REG_RO_BUS_ERROR_STS(task->irq_status) ||
|
IEP2_REG_RO_TIMEOUT_STS(task->irq_status))
|
atomic_inc(&mpp->reset_request);
|
|
mpp_task_finish(mpp_task->session, mpp_task);
|
|
mpp_debug_leave();
|
|
return IRQ_HANDLED;
|
}
|
|
static void iep2_osd_done(struct mpp_dev *mpp, struct iep_task *task)
|
{
|
int i;
|
u32 reg;
|
|
for (i = 0; i < task->output.dect_osd_cnt; ++i) {
|
reg = mpp_read(mpp, IEP2_REG_RO_OSD_AREA_X(i));
|
task->output.x_sta[i] = IEP2_REG_RO_X_STA(reg) / 16;
|
task->output.x_end[i] = IEP2_REG_RO_X_END(reg) / 16;
|
|
reg = mpp_read(mpp, IEP2_REG_RO_OSD_AREA_Y(i));
|
task->output.y_sta[i] = IEP2_REG_RO_Y_STA(reg) / 4;
|
task->output.y_end[i] = IEP2_REG_RO_Y_END(reg) / 4;
|
}
|
|
for (; i < ARRAY_SIZE(task->output.x_sta); ++i) {
|
task->output.x_sta[i] = 0;
|
task->output.x_end[i] = 0;
|
task->output.y_sta[i] = 0;
|
task->output.y_end[i] = 0;
|
}
|
}
|
|
static int iep2_finish(struct mpp_dev *mpp,
|
struct mpp_task *mpp_task)
|
{
|
struct iep_task *task = to_iep_task(mpp_task);
|
struct iep2_output *output = &task->output;
|
u32 i;
|
u32 reg;
|
|
mpp_debug_enter();
|
|
output->dect_pd_tcnt = mpp_read(mpp, IEP2_REG_RO_PD_TCNT);
|
output->dect_pd_bcnt = mpp_read(mpp, IEP2_REG_RO_PD_BCNT);
|
output->dect_ff_cur_tcnt = mpp_read(mpp, IEP2_REG_RO_FF_CUR_TCNT);
|
output->dect_ff_cur_bcnt = mpp_read(mpp, IEP2_REG_RO_FF_CUR_BCNT);
|
output->dect_ff_nxt_tcnt = mpp_read(mpp, IEP2_REG_RO_FF_NXT_TCNT);
|
output->dect_ff_nxt_bcnt = mpp_read(mpp, IEP2_REG_RO_FF_NXT_BCNT);
|
output->dect_ff_ble_tcnt = mpp_read(mpp, IEP2_REG_RO_FF_BLE_TCNT);
|
output->dect_ff_ble_bcnt = mpp_read(mpp, IEP2_REG_RO_FF_BLE_BCNT);
|
output->dect_ff_nz = mpp_read(mpp, IEP2_REG_RO_FF_COMB_NZ);
|
output->dect_ff_comb_f = mpp_read(mpp, IEP2_REG_RO_FF_COMB_F);
|
output->dect_osd_cnt = mpp_read(mpp, IEP2_REG_RO_OSD_NUM);
|
|
reg = mpp_read(mpp, IEP2_REG_RO_COMB_CNT);
|
output->out_comb_cnt = IEP2_REG_RO_OUT_COMB_CNT(reg);
|
output->out_osd_comb_cnt = IEP2_REG_RO_OUT_OSD_COMB_CNT(reg);
|
output->ff_gradt_tcnt = mpp_read(mpp, IEP2_REG_RO_FF_GRADT_TCNT);
|
output->ff_gradt_bcnt = mpp_read(mpp, IEP2_REG_RO_FF_GRADT_BCNT);
|
|
iep2_osd_done(mpp, task);
|
|
for (i = 0; i < ARRAY_SIZE(output->mv_hist); i += 2) {
|
reg = mpp_read(mpp, IEP2_REG_RO_MV_HIST_BIN(i / 2));
|
output->mv_hist[i] = IEP2_REG_RO_MV_HIST_EVEN(reg);
|
output->mv_hist[i + 1] = IEP2_REG_RO_MV_HIST_ODD(reg);
|
}
|
|
mpp_debug_leave();
|
|
return 0;
|
}
|
|
static int iep2_result(struct mpp_dev *mpp,
|
struct mpp_task *mpp_task,
|
struct mpp_task_msgs *msgs)
|
{
|
u32 i;
|
struct mpp_request *req;
|
struct iep_task *task = to_iep_task(mpp_task);
|
|
/* FIXME may overflow the kernel */
|
for (i = 0; i < task->r_req_cnt; i++) {
|
req = &task->r_reqs[i];
|
|
if (copy_to_user(req->data, (u8 *)&task->output, req->size)) {
|
mpp_err("copy_to_user reg fail\n");
|
return -EIO;
|
}
|
}
|
|
return 0;
|
}
|
|
static int iep2_free_task(struct mpp_session *session,
|
struct mpp_task *mpp_task)
|
{
|
struct iep_task *task = to_iep_task(mpp_task);
|
|
mpp_task_finalize(session, mpp_task);
|
kfree(task);
|
|
return 0;
|
}
|
|
#ifdef CONFIG_ROCKCHIP_MPP_PROC_FS
|
static int iep2_procfs_remove(struct mpp_dev *mpp)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
if (iep->procfs) {
|
proc_remove(iep->procfs);
|
iep->procfs = NULL;
|
}
|
|
return 0;
|
}
|
|
static int iep2_procfs_init(struct mpp_dev *mpp)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
iep->procfs = proc_mkdir(mpp->dev->of_node->name, mpp->srv->procfs);
|
if (IS_ERR_OR_NULL(iep->procfs)) {
|
mpp_err("failed on mkdir\n");
|
iep->procfs = NULL;
|
return -EIO;
|
}
|
|
/* for common mpp_dev options */
|
mpp_procfs_create_common(iep->procfs, mpp);
|
|
mpp_procfs_create_u32("aclk", 0644,
|
iep->procfs, &iep->aclk_info.debug_rate_hz);
|
mpp_procfs_create_u32("session_buffers", 0644,
|
iep->procfs, &mpp->session_max_buffers);
|
|
return 0;
|
}
|
#else
|
static inline int iep2_procfs_remove(struct mpp_dev *mpp)
|
{
|
return 0;
|
}
|
|
static inline int iep2_procfs_init(struct mpp_dev *mpp)
|
{
|
return 0;
|
}
|
#endif
|
|
#define IEP2_TILE_W_MAX 120
|
#define IEP2_TILE_H_MAX 272
|
|
static int iep2_init(struct mpp_dev *mpp)
|
{
|
int ret;
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_IEP2];
|
|
/* Get clock info from dtsi */
|
ret = mpp_get_clk_info(mpp, &iep->aclk_info, "aclk");
|
if (ret)
|
mpp_err("failed on clk_get aclk\n");
|
ret = mpp_get_clk_info(mpp, &iep->hclk_info, "hclk");
|
if (ret)
|
mpp_err("failed on clk_get hclk\n");
|
ret = mpp_get_clk_info(mpp, &iep->sclk_info, "sclk");
|
if (ret)
|
mpp_err("failed on clk_get sclk\n");
|
/* Set default rates */
|
mpp_set_clk_info_rate_hz(&iep->aclk_info, CLK_MODE_DEFAULT, 300 * MHZ);
|
|
iep->rst_a = mpp_reset_control_get(mpp, RST_TYPE_A, "rst_a");
|
if (!iep->rst_a)
|
mpp_err("No aclk reset resource define\n");
|
iep->rst_h = mpp_reset_control_get(mpp, RST_TYPE_H, "rst_h");
|
if (!iep->rst_h)
|
mpp_err("No hclk reset resource define\n");
|
iep->rst_s = mpp_reset_control_get(mpp, RST_TYPE_CORE, "rst_s");
|
if (!iep->rst_s)
|
mpp_err("No sclk reset resource define\n");
|
|
iep->roi.size = IEP2_TILE_W_MAX * IEP2_TILE_H_MAX;
|
iep->roi.vaddr = dma_alloc_coherent(mpp->dev, iep->roi.size,
|
&iep->roi.iova,
|
GFP_KERNEL);
|
if (iep->roi.vaddr) {
|
dev_err(mpp->dev, "allocate roi buffer failed\n");
|
//return -ENOMEM;
|
}
|
|
return 0;
|
}
|
|
static int iep2_clk_on(struct mpp_dev *mpp)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
mpp_clk_safe_enable(iep->aclk_info.clk);
|
mpp_clk_safe_enable(iep->hclk_info.clk);
|
mpp_clk_safe_enable(iep->sclk_info.clk);
|
|
return 0;
|
}
|
|
static int iep2_clk_off(struct mpp_dev *mpp)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
mpp_clk_safe_disable(iep->aclk_info.clk);
|
mpp_clk_safe_disable(iep->hclk_info.clk);
|
mpp_clk_safe_disable(iep->sclk_info.clk);
|
|
return 0;
|
}
|
|
static int iep2_set_freq(struct mpp_dev *mpp,
|
struct mpp_task *mpp_task)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
struct iep_task *task = to_iep_task(mpp_task);
|
|
mpp_clk_set_rate(&iep->aclk_info, task->clk_mode);
|
|
return 0;
|
}
|
|
static int iep2_reset(struct mpp_dev *mpp)
|
{
|
struct iep2_dev *iep = to_iep2_dev(mpp);
|
|
int ret = 0;
|
u32 rst_status = 0;
|
|
/* soft rest first */
|
mpp_write(mpp, IEP2_REG_IEP_CONFIG0, IEP2_REG_ACLK_SRESET_P);
|
ret = readl_relaxed_poll_timeout(mpp->reg_base + IEP2_REG_STATUS,
|
rst_status,
|
rst_status & IEP2_REG_ARST_FINISH_DONE,
|
0, 5);
|
if (ret) {
|
mpp_err("soft reset timeout, use cru reset\n");
|
if (iep->rst_a && iep->rst_h && iep->rst_s) {
|
/* Don't skip this or iommu won't work after reset */
|
mpp_pmu_idle_request(mpp, true);
|
mpp_safe_reset(iep->rst_a);
|
mpp_safe_reset(iep->rst_h);
|
mpp_safe_reset(iep->rst_s);
|
udelay(5);
|
mpp_safe_unreset(iep->rst_a);
|
mpp_safe_unreset(iep->rst_h);
|
mpp_safe_unreset(iep->rst_s);
|
mpp_pmu_idle_request(mpp, false);
|
}
|
}
|
|
return 0;
|
}
|
|
static struct mpp_hw_ops iep_v2_hw_ops = {
|
.init = iep2_init,
|
.clk_on = iep2_clk_on,
|
.clk_off = iep2_clk_off,
|
.set_freq = iep2_set_freq,
|
.reset = iep2_reset,
|
};
|
|
static struct mpp_dev_ops iep_v2_dev_ops = {
|
.alloc_task = iep2_alloc_task,
|
.run = iep2_run,
|
.irq = iep2_irq,
|
.isr = iep2_isr,
|
.finish = iep2_finish,
|
.result = iep2_result,
|
.free_task = iep2_free_task,
|
};
|
|
static struct mpp_hw_info iep2_hw_info = {
|
.reg_id = -1,
|
};
|
|
static const struct mpp_dev_var iep2_v2_data = {
|
.device_type = MPP_DEVICE_IEP2,
|
.hw_ops = &iep_v2_hw_ops,
|
.dev_ops = &iep_v2_dev_ops,
|
.hw_info = &iep2_hw_info,
|
};
|
|
static const struct of_device_id mpp_iep2_match[] = {
|
{
|
.compatible = "rockchip,iep-v2",
|
.data = &iep2_v2_data,
|
},
|
#ifdef CONFIG_CPU_RV1126
|
{
|
.compatible = "rockchip,rv1126-iep",
|
.data = &iep2_v2_data,
|
},
|
#endif
|
{},
|
};
|
|
static int iep2_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct iep2_dev *iep = NULL;
|
struct mpp_dev *mpp = NULL;
|
const struct of_device_id *match = NULL;
|
int ret = 0;
|
|
dev_info(dev, "probe device\n");
|
iep = devm_kzalloc(dev, sizeof(struct iep2_dev), GFP_KERNEL);
|
if (!iep)
|
return -ENOMEM;
|
|
mpp = &iep->mpp;
|
platform_set_drvdata(pdev, iep);
|
|
if (pdev->dev.of_node) {
|
match = of_match_node(mpp_iep2_match, pdev->dev.of_node);
|
if (match)
|
mpp->var = (struct mpp_dev_var *)match->data;
|
}
|
|
ret = mpp_dev_probe(mpp, pdev);
|
if (ret) {
|
dev_err(dev, "probe sub driver failed\n");
|
return -EINVAL;
|
}
|
|
ret = devm_request_threaded_irq(dev, mpp->irq,
|
mpp_dev_irq,
|
mpp_dev_isr_sched,
|
IRQF_SHARED,
|
dev_name(dev), mpp);
|
if (ret) {
|
dev_err(dev, "register interrupter runtime failed\n");
|
return -EINVAL;
|
}
|
|
mpp->session_max_buffers = IEP2_SESSION_MAX_BUFFERS;
|
iep2_procfs_init(mpp);
|
/* register current device to mpp service */
|
mpp_dev_register_srv(mpp, mpp->srv);
|
dev_info(dev, "probing finish\n");
|
|
return 0;
|
}
|
|
static int iep2_remove(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct iep2_dev *iep = platform_get_drvdata(pdev);
|
|
dma_free_coherent(dev, iep->roi.size, iep->roi.vaddr, iep->roi.iova);
|
|
dev_info(dev, "remove device\n");
|
mpp_dev_remove(&iep->mpp);
|
iep2_procfs_remove(&iep->mpp);
|
|
return 0;
|
}
|
|
static void iep2_shutdown(struct platform_device *pdev)
|
{
|
int ret;
|
int val;
|
struct device *dev = &pdev->dev;
|
struct iep2_dev *iep = platform_get_drvdata(pdev);
|
struct mpp_dev *mpp = &iep->mpp;
|
|
dev_info(dev, "shutdown device\n");
|
|
atomic_inc(&mpp->srv->shutdown_request);
|
ret = readx_poll_timeout(atomic_read,
|
&mpp->task_count,
|
val, val == 0, 20000, 200000);
|
if (ret == -ETIMEDOUT)
|
dev_err(dev, "wait total running time out\n");
|
}
|
|
static int iep2_runtime_suspend(struct device *dev)
|
{
|
struct mpp_dev *mpp = dev_get_drvdata(dev);
|
struct mpp_grf_info *info = mpp->grf_info;
|
struct mpp_taskqueue *queue = mpp->queue;
|
|
if (cpu_is_rk3528() && info && info->mem_offset) {
|
mutex_lock(&queue->ref_lock);
|
if (!atomic_dec_if_positive(&queue->runtime_cnt)) {
|
regmap_write(info->grf, info->mem_offset,
|
info->val_mem_off);
|
}
|
mutex_unlock(&queue->ref_lock);
|
}
|
|
return 0;
|
}
|
|
static int iep2_runtime_resume(struct device *dev)
|
{
|
struct mpp_dev *mpp = dev_get_drvdata(dev);
|
struct mpp_grf_info *info = mpp->grf_info;
|
struct mpp_taskqueue *queue = mpp->queue;
|
|
if (cpu_is_rk3528() && info && info->mem_offset) {
|
mutex_lock(&queue->ref_lock);
|
regmap_write(info->grf, info->mem_offset,
|
info->val_mem_on);
|
atomic_inc(&queue->runtime_cnt);
|
mutex_unlock(&queue->ref_lock);
|
}
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops iep2_pm_ops = {
|
.runtime_suspend = iep2_runtime_suspend,
|
.runtime_resume = iep2_runtime_resume,
|
};
|
|
struct platform_driver rockchip_iep2_driver = {
|
.probe = iep2_probe,
|
.remove = iep2_remove,
|
.shutdown = iep2_shutdown,
|
.driver = {
|
.name = IEP2_DRIVER_NAME,
|
.pm = &iep2_pm_ops,
|
.of_match_table = of_match_ptr(mpp_iep2_match),
|
},
|
};
|
EXPORT_SYMBOL(rockchip_iep2_driver);
|
