/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef HW_IEP_CONFIG_ADDR_H_
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#define HW_IEP_CONFIG_ADDR_H_
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#include <asm/io.h>
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/*ignore the IEP_BASE when program running in linux kernel */
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#define IEP_BASE 0x0
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#define IEP_CONFIG0 0x0000
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#define IEP_CONFIG1 0x0004
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#define IEP_STATUS 0x0008
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#define IEP_INT 0x000C
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#define IEP_FRM_START 0x0010
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#define IEP_SOFT_RST 0x0014
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#define IEP_CONF_DONE 0x0018
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#define IEP_VIR_IMG_WIDTH 0x0020
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#define IEP_IMG_SCL_FCT 0x0024
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#define IEP_SRC_IMG_SIZE 0x0028
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#define IEP_DST_IMG_SIZE 0x002C
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#define IEP_DST_IMG_WIDTH_TILE0 0x0030
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#define IEP_DST_IMG_WIDTH_TILE1 0x0034
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#define IEP_DST_IMG_WIDTH_TILE2 0x0038
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#define IEP_DST_IMG_WIDTH_TILE3 0x003C
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#define IEP_ENH_YUV_CNFG_0 0x0040
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#define IEP_ENH_YUV_CNFG_1 0x0044
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#define IEP_ENH_YUV_CNFG_2 0x0048
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#define IEP_ENH_RGB_CNFG 0x004C
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#define IEP_ENH_C_COE 0x0050
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#define IEP_SRC_ADDR_YRGB 0x0080
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#define IEP_SRC_ADDR_CBCR 0x0084
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#define IEP_SRC_ADDR_CR 0x0088
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#define IEP_SRC_ADDR_Y1 0x008C
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#define IEP_SRC_ADDR_CBCR1 0x0090
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#define IEP_SRC_ADDR_CR1 0x0094
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#define IEP_SRC_ADDR_Y_ITEMP 0x0098
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#define IEP_SRC_ADDR_CBCR_ITEMP 0x009C
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#define IEP_SRC_ADDR_CR_ITEMP 0x00A0
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#define IEP_SRC_ADDR_Y_FTEMP 0x00A4
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#define IEP_SRC_ADDR_CBCR_FTEMP 0x00A8
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#define IEP_SRC_ADDR_CR_FTEMP 0x00AC
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#define IEP_DST_ADDR_YRGB 0x00B0
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#define IEP_DST_ADDR_CBCR 0x00B4
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#define IEP_DST_ADDR_CR 0x00B8
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#define IEP_DST_ADDR_Y1 0x00BC
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#define IEP_DST_ADDR_CBCR1 0x00C0
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#define IEP_DST_ADDR_CR1 0x00C4
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#define IEP_DST_ADDR_Y_ITEMP 0x00C8
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#define IEP_DST_ADDR_CBCR_ITEMP 0x00CC
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#define IEP_DST_ADDR_CR_ITEMP 0x00D0
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#define IEP_DST_ADDR_Y_FTEMP 0x00D4
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#define IEP_DST_ADDR_CBCR_FTEMP 0x00D8
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#define IEP_DST_ADDR_CR_FTEMP 0x00DC
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#define IEP_DIL_MTN_TAB0 0x00E0
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#define IEP_DIL_MTN_TAB1 0x00E4
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#define IEP_DIL_MTN_TAB2 0x00E8
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#define IEP_DIL_MTN_TAB3 0x00EC
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#define IEP_DIL_MTN_TAB4 0x00F0
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#define IEP_DIL_MTN_TAB5 0x00F4
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#define IEP_DIL_MTN_TAB6 0x00F8
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#define IEP_DIL_MTN_TAB7 0x00FC
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#define IEP_ENH_CG_TAB 0x0100
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#define IEP_YUV_DNS_CRCT_TEMP 0x0400
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#define IEP_YUV_DNS_CRCT_SPAT 0x0800
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#define IEP_ENH_DDE_COE0 0x0C00
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#define IEP_ENH_DDE_COE1 0x0E00
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#define RAW_IEP_CONFIG0 0x0058
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#define RAW_IEP_CONFIG1 0x005C
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#define RAW_IEP_VIR_IMG_WIDTH 0x0060
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#define RAW_IEP_IMG_SCL_FCT 0x0064
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#define RAW_IEP_SRC_IMG_SIZE 0x0068
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#define RAW_IEP_DST_IMG_SIZE 0x006C
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#define RAW_IEP_ENH_YUV_CNFG_0 0x0070
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#define RAW_IEP_ENH_YUV_CNFG_1 0x0074
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#define RAW_IEP_ENH_YUV_CNFG_2 0x0078
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#define RAW_IEP_ENH_RGB_CNFG 0x007C
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#define ReadReg32(base, raddr) (__raw_readl(base + raddr))
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#define WriteReg32(base, waddr, value) (__raw_writel(value, base + waddr))
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#define ConfRegBits32(base, raddr, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
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#define MaskRegBits32(base, waddr, position, value) WriteReg32(base, waddr, (ReadReg32(base, waddr)&~(position))|(value))
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#endif
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