/*
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* HiSilicon SoC L3C uncore Hardware event counters support
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*
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* Copyright (C) 2017 Hisilicon Limited
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* Author: Anurup M <anurup.m@huawei.com>
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* Shaokun Zhang <zhangshaokun@hisilicon.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/bug.h>
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#include <linux/cpuhotplug.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include "hisi_uncore_pmu.h"
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/* L3C register definition */
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#define L3C_PERF_CTRL 0x0408
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#define L3C_INT_MASK 0x0800
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#define L3C_INT_STATUS 0x0808
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#define L3C_INT_CLEAR 0x080c
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#define L3C_EVENT_CTRL 0x1c00
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#define L3C_EVENT_TYPE0 0x1d00
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/*
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* Each counter is 48-bits and [48:63] are reserved
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* which are Read-As-Zero and Writes-Ignored.
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*/
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#define L3C_CNTR0_LOWER 0x1e00
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/* L3C has 8-counters */
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#define L3C_NR_COUNTERS 0x8
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#define L3C_PERF_CTRL_EN 0x10000
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#define L3C_EVTYPE_NONE 0xff
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/*
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* Select the counter register offset using the counter index
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*/
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static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx)
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{
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return (L3C_CNTR0_LOWER + (cntr_idx * 8));
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}
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static u64 hisi_l3c_pmu_read_counter(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc)
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{
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u32 idx = hwc->idx;
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if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
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dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
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return 0;
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}
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/* Read 64-bits and the upper 16 bits are RAZ */
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return readq(l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
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}
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static void hisi_l3c_pmu_write_counter(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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u32 idx = hwc->idx;
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if (!hisi_uncore_pmu_counter_valid(l3c_pmu, idx)) {
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dev_err(l3c_pmu->dev, "Unsupported event index:%d!\n", idx);
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return;
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}
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/* Write 64-bits and the upper 16 bits are WI */
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writeq(val, l3c_pmu->base + hisi_l3c_pmu_get_counter_offset(idx));
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}
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static void hisi_l3c_pmu_write_evtype(struct hisi_pmu *l3c_pmu, int idx,
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u32 type)
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{
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u32 reg, reg_idx, shift, val;
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/*
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* Select the appropriate event select register(L3C_EVENT_TYPE0/1).
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* There are 2 event select registers for the 8 hardware counters.
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* Event code is 8-bits and for the former 4 hardware counters,
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* L3C_EVENT_TYPE0 is chosen. For the latter 4 hardware counters,
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* L3C_EVENT_TYPE1 is chosen.
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*/
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reg = L3C_EVENT_TYPE0 + (idx / 4) * 4;
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reg_idx = idx % 4;
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shift = 8 * reg_idx;
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/* Write event code to L3C_EVENT_TYPEx Register */
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val = readl(l3c_pmu->base + reg);
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val &= ~(L3C_EVTYPE_NONE << shift);
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val |= (type << shift);
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writel(val, l3c_pmu->base + reg);
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}
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static void hisi_l3c_pmu_start_counters(struct hisi_pmu *l3c_pmu)
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{
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u32 val;
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/*
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* Set perf_enable bit in L3C_PERF_CTRL register to start counting
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* for all enabled counters.
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*/
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val = readl(l3c_pmu->base + L3C_PERF_CTRL);
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val |= L3C_PERF_CTRL_EN;
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writel(val, l3c_pmu->base + L3C_PERF_CTRL);
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}
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static void hisi_l3c_pmu_stop_counters(struct hisi_pmu *l3c_pmu)
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{
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u32 val;
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/*
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* Clear perf_enable bit in L3C_PERF_CTRL register to stop counting
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* for all enabled counters.
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*/
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val = readl(l3c_pmu->base + L3C_PERF_CTRL);
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val &= ~(L3C_PERF_CTRL_EN);
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writel(val, l3c_pmu->base + L3C_PERF_CTRL);
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}
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static void hisi_l3c_pmu_enable_counter(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Enable counter index in L3C_EVENT_CTRL register */
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val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
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val |= (1 << hwc->idx);
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writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
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}
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static void hisi_l3c_pmu_disable_counter(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Clear counter index in L3C_EVENT_CTRL register */
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val = readl(l3c_pmu->base + L3C_EVENT_CTRL);
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val &= ~(1 << hwc->idx);
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writel(val, l3c_pmu->base + L3C_EVENT_CTRL);
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}
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static void hisi_l3c_pmu_enable_counter_int(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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val = readl(l3c_pmu->base + L3C_INT_MASK);
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/* Write 0 to enable interrupt */
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val &= ~(1 << hwc->idx);
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writel(val, l3c_pmu->base + L3C_INT_MASK);
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}
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static void hisi_l3c_pmu_disable_counter_int(struct hisi_pmu *l3c_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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val = readl(l3c_pmu->base + L3C_INT_MASK);
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/* Write 1 to mask interrupt */
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val |= (1 << hwc->idx);
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writel(val, l3c_pmu->base + L3C_INT_MASK);
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}
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static irqreturn_t hisi_l3c_pmu_isr(int irq, void *dev_id)
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{
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struct hisi_pmu *l3c_pmu = dev_id;
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struct perf_event *event;
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unsigned long overflown;
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int idx;
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/* Read L3C_INT_STATUS register */
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overflown = readl(l3c_pmu->base + L3C_INT_STATUS);
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if (!overflown)
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return IRQ_NONE;
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/*
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* Find the counter index which overflowed if the bit was set
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* and handle it.
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*/
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for_each_set_bit(idx, &overflown, L3C_NR_COUNTERS) {
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/* Write 1 to clear the IRQ status flag */
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writel((1 << idx), l3c_pmu->base + L3C_INT_CLEAR);
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/* Get the corresponding event struct */
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event = l3c_pmu->pmu_events.hw_events[idx];
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if (!event)
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continue;
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hisi_uncore_pmu_event_update(event);
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hisi_uncore_pmu_set_event_period(event);
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}
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return IRQ_HANDLED;
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}
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static int hisi_l3c_pmu_init_irq(struct hisi_pmu *l3c_pmu,
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struct platform_device *pdev)
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{
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int irq, ret;
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/* Read and init IRQ */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "L3C PMU get irq fail; irq:%d\n", irq);
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return irq;
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}
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ret = devm_request_irq(&pdev->dev, irq, hisi_l3c_pmu_isr,
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IRQF_NOBALANCING | IRQF_NO_THREAD,
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dev_name(&pdev->dev), l3c_pmu);
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if (ret < 0) {
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dev_err(&pdev->dev,
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"Fail to request IRQ:%d ret:%d\n", irq, ret);
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return ret;
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}
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l3c_pmu->irq = irq;
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return 0;
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}
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static const struct acpi_device_id hisi_l3c_pmu_acpi_match[] = {
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{ "HISI0213", },
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{},
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};
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MODULE_DEVICE_TABLE(acpi, hisi_l3c_pmu_acpi_match);
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static int hisi_l3c_pmu_init_data(struct platform_device *pdev,
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struct hisi_pmu *l3c_pmu)
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{
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unsigned long long id;
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struct resource *res;
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acpi_status status;
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status = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
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"_UID", NULL, &id);
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if (ACPI_FAILURE(status))
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return -EINVAL;
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l3c_pmu->index_id = id;
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/*
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* Use the SCCL_ID and CCL_ID to identify the L3C PMU, while
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* SCCL_ID is in MPIDR[aff2] and CCL_ID is in MPIDR[aff1].
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*/
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if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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&l3c_pmu->sccl_id)) {
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dev_err(&pdev->dev, "Can not read l3c sccl-id!\n");
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return -EINVAL;
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}
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if (device_property_read_u32(&pdev->dev, "hisilicon,ccl-id",
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&l3c_pmu->ccl_id)) {
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dev_err(&pdev->dev, "Can not read l3c ccl-id!\n");
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return -EINVAL;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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l3c_pmu->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(l3c_pmu->base)) {
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dev_err(&pdev->dev, "ioremap failed for l3c_pmu resource\n");
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return PTR_ERR(l3c_pmu->base);
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}
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return 0;
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}
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static struct attribute *hisi_l3c_pmu_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-7"),
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NULL,
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};
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static const struct attribute_group hisi_l3c_pmu_format_group = {
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.name = "format",
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.attrs = hisi_l3c_pmu_format_attr,
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};
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static struct attribute *hisi_l3c_pmu_events_attr[] = {
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HISI_PMU_EVENT_ATTR(rd_cpipe, 0x00),
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HISI_PMU_EVENT_ATTR(wr_cpipe, 0x01),
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HISI_PMU_EVENT_ATTR(rd_hit_cpipe, 0x02),
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HISI_PMU_EVENT_ATTR(wr_hit_cpipe, 0x03),
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HISI_PMU_EVENT_ATTR(victim_num, 0x04),
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HISI_PMU_EVENT_ATTR(rd_spipe, 0x20),
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HISI_PMU_EVENT_ATTR(wr_spipe, 0x21),
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HISI_PMU_EVENT_ATTR(rd_hit_spipe, 0x22),
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HISI_PMU_EVENT_ATTR(wr_hit_spipe, 0x23),
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HISI_PMU_EVENT_ATTR(back_invalid, 0x29),
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HISI_PMU_EVENT_ATTR(retry_cpu, 0x40),
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HISI_PMU_EVENT_ATTR(retry_ring, 0x41),
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HISI_PMU_EVENT_ATTR(prefetch_drop, 0x42),
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NULL,
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};
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static const struct attribute_group hisi_l3c_pmu_events_group = {
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.name = "events",
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.attrs = hisi_l3c_pmu_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_l3c_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static const struct attribute_group hisi_l3c_pmu_cpumask_attr_group = {
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.attrs = hisi_l3c_pmu_cpumask_attrs,
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};
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static const struct attribute_group *hisi_l3c_pmu_attr_groups[] = {
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&hisi_l3c_pmu_format_group,
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&hisi_l3c_pmu_events_group,
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&hisi_l3c_pmu_cpumask_attr_group,
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NULL,
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};
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static const struct hisi_uncore_ops hisi_uncore_l3c_ops = {
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.write_evtype = hisi_l3c_pmu_write_evtype,
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.get_event_idx = hisi_uncore_pmu_get_event_idx,
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.start_counters = hisi_l3c_pmu_start_counters,
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.stop_counters = hisi_l3c_pmu_stop_counters,
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.enable_counter = hisi_l3c_pmu_enable_counter,
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.disable_counter = hisi_l3c_pmu_disable_counter,
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.enable_counter_int = hisi_l3c_pmu_enable_counter_int,
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.disable_counter_int = hisi_l3c_pmu_disable_counter_int,
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.write_counter = hisi_l3c_pmu_write_counter,
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.read_counter = hisi_l3c_pmu_read_counter,
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};
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static int hisi_l3c_pmu_dev_probe(struct platform_device *pdev,
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struct hisi_pmu *l3c_pmu)
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{
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int ret;
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ret = hisi_l3c_pmu_init_data(pdev, l3c_pmu);
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if (ret)
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return ret;
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ret = hisi_l3c_pmu_init_irq(l3c_pmu, pdev);
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if (ret)
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return ret;
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l3c_pmu->num_counters = L3C_NR_COUNTERS;
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l3c_pmu->counter_bits = 48;
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l3c_pmu->ops = &hisi_uncore_l3c_ops;
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l3c_pmu->dev = &pdev->dev;
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l3c_pmu->on_cpu = -1;
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l3c_pmu->check_event = 0x59;
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return 0;
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}
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static int hisi_l3c_pmu_probe(struct platform_device *pdev)
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{
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struct hisi_pmu *l3c_pmu;
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char *name;
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int ret;
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l3c_pmu = devm_kzalloc(&pdev->dev, sizeof(*l3c_pmu), GFP_KERNEL);
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if (!l3c_pmu)
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return -ENOMEM;
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platform_set_drvdata(pdev, l3c_pmu);
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ret = hisi_l3c_pmu_dev_probe(pdev, l3c_pmu);
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if (ret)
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return ret;
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ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
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&l3c_pmu->node);
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if (ret) {
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dev_err(&pdev->dev, "Error %d registering hotplug\n", ret);
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return ret;
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}
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name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_l3c%u",
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l3c_pmu->sccl_id, l3c_pmu->index_id);
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l3c_pmu->pmu = (struct pmu) {
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.name = name,
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.task_ctx_nr = perf_invalid_context,
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.event_init = hisi_uncore_pmu_event_init,
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.pmu_enable = hisi_uncore_pmu_enable,
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.pmu_disable = hisi_uncore_pmu_disable,
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.add = hisi_uncore_pmu_add,
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.del = hisi_uncore_pmu_del,
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = hisi_l3c_pmu_attr_groups,
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};
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ret = perf_pmu_register(&l3c_pmu->pmu, name, -1);
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if (ret) {
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dev_err(l3c_pmu->dev, "L3C PMU register failed!\n");
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cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
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&l3c_pmu->node);
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}
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return ret;
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}
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static int hisi_l3c_pmu_remove(struct platform_device *pdev)
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{
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struct hisi_pmu *l3c_pmu = platform_get_drvdata(pdev);
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perf_pmu_unregister(&l3c_pmu->pmu);
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cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
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&l3c_pmu->node);
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return 0;
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}
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static struct platform_driver hisi_l3c_pmu_driver = {
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.driver = {
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.name = "hisi_l3c_pmu",
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.acpi_match_table = ACPI_PTR(hisi_l3c_pmu_acpi_match),
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},
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.probe = hisi_l3c_pmu_probe,
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.remove = hisi_l3c_pmu_remove,
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};
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static int __init hisi_l3c_pmu_module_init(void)
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{
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int ret;
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ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE,
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"AP_PERF_ARM_HISI_L3_ONLINE",
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hisi_uncore_pmu_online_cpu,
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hisi_uncore_pmu_offline_cpu);
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if (ret) {
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pr_err("L3C PMU: Error setup hotplug, ret = %d\n", ret);
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return ret;
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}
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ret = platform_driver_register(&hisi_l3c_pmu_driver);
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if (ret)
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cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
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return ret;
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}
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module_init(hisi_l3c_pmu_module_init);
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static void __exit hisi_l3c_pmu_module_exit(void)
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{
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platform_driver_unregister(&hisi_l3c_pmu_driver);
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cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_L3_ONLINE);
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}
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module_exit(hisi_l3c_pmu_module_exit);
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MODULE_DESCRIPTION("HiSilicon SoC L3C uncore PMU driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
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MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
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