/*
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* HiSilicon SoC DDRC uncore Hardware event counters support
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*
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* Copyright (C) 2017 Hisilicon Limited
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* Author: Shaokun Zhang <zhangshaokun@hisilicon.com>
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* Anurup M <anurup.m@huawei.com>
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*
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* This code is based on the uncore PMUs like arm-cci and arm-ccn.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/acpi.h>
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#include <linux/bug.h>
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#include <linux/cpuhotplug.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include "hisi_uncore_pmu.h"
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/* DDRC register definition */
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#define DDRC_PERF_CTRL 0x010
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#define DDRC_FLUX_WR 0x380
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#define DDRC_FLUX_RD 0x384
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#define DDRC_FLUX_WCMD 0x388
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#define DDRC_FLUX_RCMD 0x38c
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#define DDRC_PRE_CMD 0x3c0
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#define DDRC_ACT_CMD 0x3c4
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#define DDRC_RNK_CHG 0x3cc
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#define DDRC_RW_CHG 0x3d0
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#define DDRC_EVENT_CTRL 0x6C0
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#define DDRC_INT_MASK 0x6c8
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#define DDRC_INT_STATUS 0x6cc
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#define DDRC_INT_CLEAR 0x6d0
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/* DDRC has 8-counters */
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#define DDRC_NR_COUNTERS 0x8
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#define DDRC_PERF_CTRL_EN 0x2
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/*
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* For DDRC PMU, there are eight-events and every event has been mapped
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* to fixed-purpose counters which register offset is not consistent.
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* Therefore there is no write event type and we assume that event
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* code (0 to 7) is equal to counter index in PMU driver.
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*/
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#define GET_DDRC_EVENTID(hwc) (hwc->config_base & 0x7)
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static const u32 ddrc_reg_off[] = {
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DDRC_FLUX_WR, DDRC_FLUX_RD, DDRC_FLUX_WCMD, DDRC_FLUX_RCMD,
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DDRC_PRE_CMD, DDRC_ACT_CMD, DDRC_RNK_CHG, DDRC_RW_CHG
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};
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/*
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* Select the counter register offset using the counter index.
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* In DDRC there are no programmable counter, the count
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* is readed form the statistics counter register itself.
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*/
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static u32 hisi_ddrc_pmu_get_counter_offset(int cntr_idx)
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{
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return ddrc_reg_off[cntr_idx];
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}
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static u64 hisi_ddrc_pmu_read_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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/* Use event code as counter index */
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u32 idx = GET_DDRC_EVENTID(hwc);
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if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
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dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
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return 0;
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}
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return readl(ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
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}
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static void hisi_ddrc_pmu_write_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc, u64 val)
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{
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u32 idx = GET_DDRC_EVENTID(hwc);
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if (!hisi_uncore_pmu_counter_valid(ddrc_pmu, idx)) {
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dev_err(ddrc_pmu->dev, "Unsupported event index:%d!\n", idx);
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return;
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}
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writel((u32)val,
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ddrc_pmu->base + hisi_ddrc_pmu_get_counter_offset(idx));
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}
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/*
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* For DDRC PMU, event has been mapped to fixed-purpose counter by hardware,
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* so there is no need to write event type.
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*/
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static void hisi_ddrc_pmu_write_evtype(struct hisi_pmu *hha_pmu, int idx,
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u32 type)
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{
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}
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static void hisi_ddrc_pmu_start_counters(struct hisi_pmu *ddrc_pmu)
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{
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u32 val;
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/* Set perf_enable in DDRC_PERF_CTRL to start event counting */
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val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
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val |= DDRC_PERF_CTRL_EN;
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writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
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}
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static void hisi_ddrc_pmu_stop_counters(struct hisi_pmu *ddrc_pmu)
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{
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u32 val;
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/* Clear perf_enable in DDRC_PERF_CTRL to stop event counting */
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val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
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val &= ~DDRC_PERF_CTRL_EN;
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writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
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}
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static void hisi_ddrc_pmu_enable_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Set counter index(event code) in DDRC_EVENT_CTRL register */
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val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
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val |= (1 << GET_DDRC_EVENTID(hwc));
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writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
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}
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static void hisi_ddrc_pmu_disable_counter(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Clear counter index(event code) in DDRC_EVENT_CTRL register */
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val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
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val &= ~(1 << GET_DDRC_EVENTID(hwc));
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writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
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}
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static int hisi_ddrc_pmu_get_event_idx(struct perf_event *event)
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{
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struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
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unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
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struct hw_perf_event *hwc = &event->hw;
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/* For DDRC PMU, we use event code as counter index */
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int idx = GET_DDRC_EVENTID(hwc);
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if (test_bit(idx, used_mask))
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return -EAGAIN;
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set_bit(idx, used_mask);
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return idx;
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}
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static void hisi_ddrc_pmu_enable_counter_int(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 0 to enable interrupt */
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val = readl(ddrc_pmu->base + DDRC_INT_MASK);
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val &= ~(1 << GET_DDRC_EVENTID(hwc));
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writel(val, ddrc_pmu->base + DDRC_INT_MASK);
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}
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static void hisi_ddrc_pmu_disable_counter_int(struct hisi_pmu *ddrc_pmu,
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struct hw_perf_event *hwc)
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{
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u32 val;
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/* Write 1 to mask interrupt */
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val = readl(ddrc_pmu->base + DDRC_INT_MASK);
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val |= (1 << GET_DDRC_EVENTID(hwc));
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writel(val, ddrc_pmu->base + DDRC_INT_MASK);
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}
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static irqreturn_t hisi_ddrc_pmu_isr(int irq, void *dev_id)
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{
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struct hisi_pmu *ddrc_pmu = dev_id;
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struct perf_event *event;
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unsigned long overflown;
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int idx;
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/* Read the DDRC_INT_STATUS register */
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overflown = readl(ddrc_pmu->base + DDRC_INT_STATUS);
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if (!overflown)
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return IRQ_NONE;
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/*
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* Find the counter index which overflowed if the bit was set
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* and handle it
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*/
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for_each_set_bit(idx, &overflown, DDRC_NR_COUNTERS) {
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/* Write 1 to clear the IRQ status flag */
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writel((1 << idx), ddrc_pmu->base + DDRC_INT_CLEAR);
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/* Get the corresponding event struct */
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event = ddrc_pmu->pmu_events.hw_events[idx];
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if (!event)
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continue;
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hisi_uncore_pmu_event_update(event);
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hisi_uncore_pmu_set_event_period(event);
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}
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return IRQ_HANDLED;
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}
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static int hisi_ddrc_pmu_init_irq(struct hisi_pmu *ddrc_pmu,
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struct platform_device *pdev)
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{
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int irq, ret;
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/* Read and init IRQ */
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "DDRC PMU get irq fail; irq:%d\n", irq);
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return irq;
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}
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ret = devm_request_irq(&pdev->dev, irq, hisi_ddrc_pmu_isr,
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IRQF_NOBALANCING | IRQF_NO_THREAD,
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dev_name(&pdev->dev), ddrc_pmu);
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if (ret < 0) {
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dev_err(&pdev->dev,
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"Fail to request IRQ:%d ret:%d\n", irq, ret);
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return ret;
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}
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ddrc_pmu->irq = irq;
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return 0;
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}
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static const struct acpi_device_id hisi_ddrc_pmu_acpi_match[] = {
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{ "HISI0233", },
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{},
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};
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MODULE_DEVICE_TABLE(acpi, hisi_ddrc_pmu_acpi_match);
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static int hisi_ddrc_pmu_init_data(struct platform_device *pdev,
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struct hisi_pmu *ddrc_pmu)
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{
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struct resource *res;
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/*
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* Use the SCCL_ID and DDRC channel ID to identify the
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* DDRC PMU, while SCCL_ID is in MPIDR[aff2].
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*/
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if (device_property_read_u32(&pdev->dev, "hisilicon,ch-id",
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&ddrc_pmu->index_id)) {
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dev_err(&pdev->dev, "Can not read ddrc channel-id!\n");
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return -EINVAL;
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}
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if (device_property_read_u32(&pdev->dev, "hisilicon,scl-id",
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&ddrc_pmu->sccl_id)) {
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dev_err(&pdev->dev, "Can not read ddrc sccl-id!\n");
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return -EINVAL;
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}
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/* DDRC PMUs only share the same SCCL */
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ddrc_pmu->ccl_id = -1;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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ddrc_pmu->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(ddrc_pmu->base)) {
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dev_err(&pdev->dev, "ioremap failed for ddrc_pmu resource\n");
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return PTR_ERR(ddrc_pmu->base);
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}
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return 0;
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}
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static struct attribute *hisi_ddrc_pmu_format_attr[] = {
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HISI_PMU_FORMAT_ATTR(event, "config:0-4"),
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NULL,
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};
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static const struct attribute_group hisi_ddrc_pmu_format_group = {
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.name = "format",
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.attrs = hisi_ddrc_pmu_format_attr,
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};
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static struct attribute *hisi_ddrc_pmu_events_attr[] = {
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HISI_PMU_EVENT_ATTR(flux_wr, 0x00),
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HISI_PMU_EVENT_ATTR(flux_rd, 0x01),
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HISI_PMU_EVENT_ATTR(flux_wcmd, 0x02),
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HISI_PMU_EVENT_ATTR(flux_rcmd, 0x03),
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HISI_PMU_EVENT_ATTR(pre_cmd, 0x04),
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HISI_PMU_EVENT_ATTR(act_cmd, 0x05),
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HISI_PMU_EVENT_ATTR(rnk_chg, 0x06),
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HISI_PMU_EVENT_ATTR(rw_chg, 0x07),
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NULL,
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};
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static const struct attribute_group hisi_ddrc_pmu_events_group = {
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.name = "events",
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.attrs = hisi_ddrc_pmu_events_attr,
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};
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static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
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static struct attribute *hisi_ddrc_pmu_cpumask_attrs[] = {
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&dev_attr_cpumask.attr,
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NULL,
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};
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static const struct attribute_group hisi_ddrc_pmu_cpumask_attr_group = {
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.attrs = hisi_ddrc_pmu_cpumask_attrs,
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};
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static const struct attribute_group *hisi_ddrc_pmu_attr_groups[] = {
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&hisi_ddrc_pmu_format_group,
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&hisi_ddrc_pmu_events_group,
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&hisi_ddrc_pmu_cpumask_attr_group,
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NULL,
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};
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static const struct hisi_uncore_ops hisi_uncore_ddrc_ops = {
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.write_evtype = hisi_ddrc_pmu_write_evtype,
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.get_event_idx = hisi_ddrc_pmu_get_event_idx,
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.start_counters = hisi_ddrc_pmu_start_counters,
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.stop_counters = hisi_ddrc_pmu_stop_counters,
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.enable_counter = hisi_ddrc_pmu_enable_counter,
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.disable_counter = hisi_ddrc_pmu_disable_counter,
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.enable_counter_int = hisi_ddrc_pmu_enable_counter_int,
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.disable_counter_int = hisi_ddrc_pmu_disable_counter_int,
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.write_counter = hisi_ddrc_pmu_write_counter,
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.read_counter = hisi_ddrc_pmu_read_counter,
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};
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static int hisi_ddrc_pmu_dev_probe(struct platform_device *pdev,
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struct hisi_pmu *ddrc_pmu)
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{
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int ret;
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ret = hisi_ddrc_pmu_init_data(pdev, ddrc_pmu);
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if (ret)
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return ret;
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ret = hisi_ddrc_pmu_init_irq(ddrc_pmu, pdev);
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if (ret)
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return ret;
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ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
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ddrc_pmu->counter_bits = 32;
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ddrc_pmu->ops = &hisi_uncore_ddrc_ops;
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ddrc_pmu->dev = &pdev->dev;
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ddrc_pmu->on_cpu = -1;
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ddrc_pmu->check_event = 7;
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return 0;
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}
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static int hisi_ddrc_pmu_probe(struct platform_device *pdev)
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{
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struct hisi_pmu *ddrc_pmu;
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char *name;
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int ret;
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ddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddrc_pmu), GFP_KERNEL);
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if (!ddrc_pmu)
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return -ENOMEM;
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platform_set_drvdata(pdev, ddrc_pmu);
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ret = hisi_ddrc_pmu_dev_probe(pdev, ddrc_pmu);
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if (ret)
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return ret;
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ret = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
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&ddrc_pmu->node);
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if (ret) {
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dev_err(&pdev->dev, "Error %d registering hotplug;\n", ret);
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return ret;
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}
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name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "hisi_sccl%u_ddrc%u",
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ddrc_pmu->sccl_id, ddrc_pmu->index_id);
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ddrc_pmu->pmu = (struct pmu) {
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.name = name,
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.task_ctx_nr = perf_invalid_context,
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.event_init = hisi_uncore_pmu_event_init,
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.pmu_enable = hisi_uncore_pmu_enable,
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.pmu_disable = hisi_uncore_pmu_disable,
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.add = hisi_uncore_pmu_add,
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.del = hisi_uncore_pmu_del,
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.start = hisi_uncore_pmu_start,
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.stop = hisi_uncore_pmu_stop,
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.read = hisi_uncore_pmu_read,
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.attr_groups = hisi_ddrc_pmu_attr_groups,
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};
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ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
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if (ret) {
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dev_err(ddrc_pmu->dev, "DDRC PMU register failed!\n");
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cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
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&ddrc_pmu->node);
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}
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return ret;
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}
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static int hisi_ddrc_pmu_remove(struct platform_device *pdev)
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{
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struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
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perf_pmu_unregister(&ddrc_pmu->pmu);
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cpuhp_state_remove_instance(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
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&ddrc_pmu->node);
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return 0;
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}
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static struct platform_driver hisi_ddrc_pmu_driver = {
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.driver = {
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.name = "hisi_ddrc_pmu",
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.acpi_match_table = ACPI_PTR(hisi_ddrc_pmu_acpi_match),
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},
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.probe = hisi_ddrc_pmu_probe,
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.remove = hisi_ddrc_pmu_remove,
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};
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static int __init hisi_ddrc_pmu_module_init(void)
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{
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int ret;
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ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE,
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"AP_PERF_ARM_HISI_DDRC_ONLINE",
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hisi_uncore_pmu_online_cpu,
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hisi_uncore_pmu_offline_cpu);
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if (ret) {
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pr_err("DDRC PMU: setup hotplug, ret = %d\n", ret);
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return ret;
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}
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ret = platform_driver_register(&hisi_ddrc_pmu_driver);
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if (ret)
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cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
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return ret;
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}
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module_init(hisi_ddrc_pmu_module_init);
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static void __exit hisi_ddrc_pmu_module_exit(void)
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{
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platform_driver_unregister(&hisi_ddrc_pmu_driver);
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cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE);
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}
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module_exit(hisi_ddrc_pmu_module_exit);
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MODULE_DESCRIPTION("HiSilicon SoC DDRC uncore PMU driver");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Shaokun Zhang <zhangshaokun@hisilicon.com>");
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MODULE_AUTHOR("Anurup M <anurup.m@huawei.com>");
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