/*
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* Copyright (C) 2008
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* Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
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*
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* Copyright (C) 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _IPU_INTERN_H_
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#define _IPU_INTERN_H_
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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/* IPU Common registers */
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#define IPU_CONF 0x00
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#define IPU_CHA_BUF0_RDY 0x04
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#define IPU_CHA_BUF1_RDY 0x08
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#define IPU_CHA_DB_MODE_SEL 0x0C
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#define IPU_CHA_CUR_BUF 0x10
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#define IPU_FS_PROC_FLOW 0x14
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#define IPU_FS_DISP_FLOW 0x18
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#define IPU_TASKS_STAT 0x1C
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#define IPU_IMA_ADDR 0x20
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#define IPU_IMA_DATA 0x24
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#define IPU_INT_CTRL_1 0x28
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#define IPU_INT_CTRL_2 0x2C
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#define IPU_INT_CTRL_3 0x30
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#define IPU_INT_CTRL_4 0x34
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#define IPU_INT_CTRL_5 0x38
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#define IPU_INT_STAT_1 0x3C
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#define IPU_INT_STAT_2 0x40
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#define IPU_INT_STAT_3 0x44
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#define IPU_INT_STAT_4 0x48
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#define IPU_INT_STAT_5 0x4C
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#define IPU_BRK_CTRL_1 0x50
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#define IPU_BRK_CTRL_2 0x54
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#define IPU_BRK_STAT 0x58
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#define IPU_DIAGB_CTRL 0x5C
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/* IPU_CONF Register bits */
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#define IPU_CONF_CSI_EN 0x00000001
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#define IPU_CONF_IC_EN 0x00000002
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#define IPU_CONF_ROT_EN 0x00000004
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#define IPU_CONF_PF_EN 0x00000008
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#define IPU_CONF_SDC_EN 0x00000010
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#define IPU_CONF_ADC_EN 0x00000020
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#define IPU_CONF_DI_EN 0x00000040
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#define IPU_CONF_DU_EN 0x00000080
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#define IPU_CONF_PXL_ENDIAN 0x00000100
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/* Image Converter Registers */
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#define IC_CONF 0x88
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#define IC_PRP_ENC_RSC 0x8C
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#define IC_PRP_VF_RSC 0x90
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#define IC_PP_RSC 0x94
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#define IC_CMBP_1 0x98
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#define IC_CMBP_2 0x9C
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#define PF_CONF 0xA0
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#define IDMAC_CONF 0xA4
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#define IDMAC_CHA_EN 0xA8
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#define IDMAC_CHA_PRI 0xAC
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#define IDMAC_CHA_BUSY 0xB0
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/* Image Converter Register bits */
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#define IC_CONF_PRPENC_EN 0x00000001
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#define IC_CONF_PRPENC_CSC1 0x00000002
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#define IC_CONF_PRPENC_ROT_EN 0x00000004
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#define IC_CONF_PRPVF_EN 0x00000100
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#define IC_CONF_PRPVF_CSC1 0x00000200
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#define IC_CONF_PRPVF_CSC2 0x00000400
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#define IC_CONF_PRPVF_CMB 0x00000800
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#define IC_CONF_PRPVF_ROT_EN 0x00001000
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#define IC_CONF_PP_EN 0x00010000
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#define IC_CONF_PP_CSC1 0x00020000
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#define IC_CONF_PP_CSC2 0x00040000
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#define IC_CONF_PP_CMB 0x00080000
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#define IC_CONF_PP_ROT_EN 0x00100000
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#define IC_CONF_IC_GLB_LOC_A 0x10000000
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#define IC_CONF_KEY_COLOR_EN 0x20000000
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#define IC_CONF_RWS_EN 0x40000000
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#define IC_CONF_CSI_MEM_WR_EN 0x80000000
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#define IDMA_CHAN_INVALID 0x000000FF
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#define IDMA_IC_0 0x00000001
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#define IDMA_IC_1 0x00000002
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#define IDMA_IC_2 0x00000004
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#define IDMA_IC_3 0x00000008
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#define IDMA_IC_4 0x00000010
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#define IDMA_IC_5 0x00000020
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#define IDMA_IC_6 0x00000040
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#define IDMA_IC_7 0x00000080
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#define IDMA_IC_8 0x00000100
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#define IDMA_IC_9 0x00000200
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#define IDMA_IC_10 0x00000400
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#define IDMA_IC_11 0x00000800
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#define IDMA_IC_12 0x00001000
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#define IDMA_IC_13 0x00002000
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#define IDMA_SDC_BG 0x00004000
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#define IDMA_SDC_FG 0x00008000
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#define IDMA_SDC_MASK 0x00010000
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#define IDMA_SDC_PARTIAL 0x00020000
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#define IDMA_ADC_SYS1_WR 0x00040000
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#define IDMA_ADC_SYS2_WR 0x00080000
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#define IDMA_ADC_SYS1_CMD 0x00100000
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#define IDMA_ADC_SYS2_CMD 0x00200000
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#define IDMA_ADC_SYS1_RD 0x00400000
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#define IDMA_ADC_SYS2_RD 0x00800000
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#define IDMA_PF_QP 0x01000000
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#define IDMA_PF_BSP 0x02000000
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#define IDMA_PF_Y_IN 0x04000000
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#define IDMA_PF_U_IN 0x08000000
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#define IDMA_PF_V_IN 0x10000000
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#define IDMA_PF_Y_OUT 0x20000000
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#define IDMA_PF_U_OUT 0x40000000
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#define IDMA_PF_V_OUT 0x80000000
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#define TSTAT_PF_H264_PAUSE 0x00000001
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#define TSTAT_CSI2MEM_MASK 0x0000000C
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#define TSTAT_CSI2MEM_OFFSET 2
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#define TSTAT_VF_MASK 0x00000600
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#define TSTAT_VF_OFFSET 9
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#define TSTAT_VF_ROT_MASK 0x000C0000
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#define TSTAT_VF_ROT_OFFSET 18
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#define TSTAT_ENC_MASK 0x00000180
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#define TSTAT_ENC_OFFSET 7
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#define TSTAT_ENC_ROT_MASK 0x00030000
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#define TSTAT_ENC_ROT_OFFSET 16
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#define TSTAT_PP_MASK 0x00001800
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#define TSTAT_PP_OFFSET 11
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#define TSTAT_PP_ROT_MASK 0x00300000
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#define TSTAT_PP_ROT_OFFSET 20
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#define TSTAT_PF_MASK 0x00C00000
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#define TSTAT_PF_OFFSET 22
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#define TSTAT_ADCSYS1_MASK 0x03000000
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#define TSTAT_ADCSYS1_OFFSET 24
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#define TSTAT_ADCSYS2_MASK 0x0C000000
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#define TSTAT_ADCSYS2_OFFSET 26
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#define TASK_STAT_IDLE 0
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#define TASK_STAT_ACTIVE 1
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#define TASK_STAT_WAIT4READY 2
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struct idmac {
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struct dma_device dma;
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};
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struct ipu {
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void __iomem *reg_ipu;
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void __iomem *reg_ic;
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unsigned int irq_fn; /* IPU Function IRQ to the CPU */
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unsigned int irq_err; /* IPU Error IRQ to the CPU */
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unsigned int irq_base; /* Beginning of the IPU IRQ range */
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unsigned long channel_init_mask;
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spinlock_t lock;
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struct clk *ipu_clk;
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struct device *dev;
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struct idmac idmac;
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struct idmac_channel channel[IPU_CHANNELS_NUM];
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struct tasklet_struct tasklet;
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};
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#define to_idmac(d) container_of(d, struct idmac, dma)
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extern int ipu_irq_attach_irq(struct ipu *ipu, struct platform_device *dev);
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extern void ipu_irq_detach_irq(struct ipu *ipu, struct platform_device *dev);
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extern bool ipu_irq_status(uint32_t irq);
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extern int ipu_irq_map(unsigned int source);
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extern int ipu_irq_unmap(unsigned int source);
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#endif
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