// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/regmap.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include "clk.h"
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#define div_mask(width) ((1 << (width)) - 1)
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static unsigned long clk_dclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int val;
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val = clk_readl(divider->reg) >> divider->shift;
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val &= div_mask(divider->width);
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return DIV_ROUND_UP_ULL(((u64)parent_rate), val + 1);
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}
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static long clk_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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int div, maxdiv = div_mask(divider->width) + 1;
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div = DIV_ROUND_UP_ULL(divider->max_prate, rate);
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if (div % 2)
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div = __rounddown_pow_of_two(div);
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div = div > maxdiv ? maxdiv : div;
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*prate = div * rate;
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return rate;
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}
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static int clk_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_divider *divider = to_clk_divider(hw);
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unsigned int value;
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unsigned long flags = 0;
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u32 val;
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value = divider_get_val(rate, parent_rate, divider->table,
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divider->width, divider->flags);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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else
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__acquire(divider->lock);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider->width) << (divider->shift + 16);
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} else {
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val = clk_readl(divider->reg);
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val &= ~(div_mask(divider->width) << divider->shift);
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}
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val |= value << divider->shift;
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clk_writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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else
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__release(divider->lock);
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return 0;
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}
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const struct clk_ops clk_dclk_divider_ops = {
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.recalc_rate = clk_dclk_recalc_rate,
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.round_rate = clk_dclk_round_rate,
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.set_rate = clk_dclk_set_rate,
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};
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EXPORT_SYMBOL_GPL(clk_dclk_divider_ops);
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/**
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* Register a clock branch.
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* Most clock branches have a form like
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*
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* src1 --|--\
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* |M |--[GATE]-[DIV]-
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* src2 --|--/
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*
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* sometimes without one of those components.
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*/
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struct clk *rockchip_clk_register_dclk_branch(const char *name,
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const char *const *parent_names,
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u8 num_parents,
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void __iomem *base,
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int muxdiv_offset, u8 mux_shift,
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u8 mux_width, u8 mux_flags,
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int div_offset, u8 div_shift,
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u8 div_width, u8 div_flags,
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struct clk_div_table *div_table,
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int gate_offset,
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u8 gate_shift, u8 gate_flags,
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unsigned long flags,
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unsigned long max_prate,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
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*gate_ops = NULL;
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if (num_parents > 1) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->reg = base + muxdiv_offset;
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mux->shift = mux_shift;
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mux->mask = BIT(mux_width) - 1;
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mux->flags = mux_flags;
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mux->lock = lock;
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mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
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: &clk_mux_ops;
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}
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if (gate_offset >= 0) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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goto err_gate;
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gate->flags = gate_flags;
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gate->reg = base + gate_offset;
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gate->bit_idx = gate_shift;
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gate->lock = lock;
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gate_ops = &clk_gate_ops;
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}
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if (div_width > 0) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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goto err_div;
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div->flags = div_flags;
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if (div_offset)
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div->reg = base + div_offset;
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else
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div->reg = base + muxdiv_offset;
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div->shift = div_shift;
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div->width = div_width;
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div->lock = lock;
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div->max_prate = max_prate;
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div_ops = &clk_dclk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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return clk;
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err_div:
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kfree(gate);
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err_gate:
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kfree(mux);
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return ERR_PTR(-ENOMEM);
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}
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