/*
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* Marvell EBU SoC common clock handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __CLK_MVEBU_COMMON_H_
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#define __CLK_MVEBU_COMMON_H_
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#include <linux/kernel.h>
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extern spinlock_t ctrl_gating_lock;
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struct device_node;
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struct coreclk_ratio {
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int id;
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const char *name;
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};
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struct coreclk_soc_desc {
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u32 (*get_tclk_freq)(void __iomem *sar);
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u32 (*get_cpu_freq)(void __iomem *sar);
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void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
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u32 (*get_refclk_freq)(void __iomem *sar);
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bool (*is_sscg_enabled)(void __iomem *sar);
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u32 (*fix_sscg_deviation)(u32 system_clk);
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const struct coreclk_ratio *ratios;
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int num_ratios;
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};
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struct clk_gating_soc_desc {
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const char *name;
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const char *parent;
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int bit_idx;
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unsigned long flags;
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};
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void __init mvebu_coreclk_setup(struct device_node *np,
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const struct coreclk_soc_desc *desc);
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void __init mvebu_clk_gating_setup(struct device_node *np,
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const struct clk_gating_soc_desc *desc);
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/*
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* This function is shared among the Kirkwood, Armada 370, Armada XP
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* and Armada 375 SoC
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*/
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u32 kirkwood_fix_sscg_deviation(u32 system_clk);
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#endif
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