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| // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
| /*
| * Copyright : STMicroelectronics 2018
| */
|
| #include <dt-bindings/clock/stm32mp1-clksrc.h>
| #include "stm32mp157-u-boot.dtsi"
| #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
|
| / {
| aliases {
| i2c3 = &i2c4;
| mmc0 = &sdmmc1;
| usb0 = &usbotg_hs;
| };
| config {
| u-boot,boot-led = "heartbeat";
| u-boot,error-led = "error";
| st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
| };
| led {
| red {
| label = "error";
| gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
| default-state = "off";
| status = "okay";
| };
|
| blue {
| default-state = "on";
| };
| };
| };
|
| &adc {
| pinctrl-names = "default";
| pinctrl-0 = <&adc12_usb_pwr_pins_a>;
| vdd-supply = <&vdd>;
| vdda-supply = <&vdd>;
| vref-supply = <&vrefbuf>;
| status = "okay";
| adc1: adc@0 {
| /*
| * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in18 & in19.
| * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C:
| * 5 * (56 + 47kOhms) * 5pF => 2.5us.
| * Use arbitrary margin here (e.g. 5µs).
| */
| st,min-sample-time-nsecs = <5000>;
| /* ANA0, ANA1, USB Type-C CC1 & CC2 */
| st,adc-channels = <0 1 18 19>;
| status = "okay";
| };
| };
|
| &clk_hse {
| st,digbypass;
| };
|
| &i2c4 {
| u-boot,dm-pre-reloc;
| };
|
| &i2c4_pins_a {
| u-boot,dm-pre-reloc;
| pins {
| u-boot,dm-pre-reloc;
| };
| };
|
| &pmic {
| u-boot,dm-pre-reloc;
| };
|
| &rcc {
| st,clksrc = <
| CLK_MPU_PLL1P
| CLK_AXI_PLL2P
| CLK_MCU_PLL3P
| CLK_PLL12_HSE
| CLK_PLL3_HSE
| CLK_PLL4_HSE
| CLK_RTC_LSE
| CLK_MCO1_DISABLED
| CLK_MCO2_DISABLED
| >;
|
| st,clkdiv = <
| 1 /*MPU*/
| 0 /*AXI*/
| 0 /*MCU*/
| 1 /*APB1*/
| 1 /*APB2*/
| 1 /*APB3*/
| 1 /*APB4*/
| 2 /*APB5*/
| 23 /*RTC*/
| 0 /*MCO1*/
| 0 /*MCO2*/
| >;
|
| st,pkcs = <
| CLK_CKPER_HSE
| CLK_FMC_ACLK
| CLK_QSPI_ACLK
| CLK_ETH_DISABLED
| CLK_SDMMC12_PLL4P
| CLK_DSI_DSIPLL
| CLK_STGEN_HSE
| CLK_USBPHY_HSE
| CLK_SPI2S1_PLL3Q
| CLK_SPI2S23_PLL3Q
| CLK_SPI45_HSI
| CLK_SPI6_HSI
| CLK_I2C46_HSI
| CLK_SDMMC3_PLL4P
| CLK_USBO_USBPHY
| CLK_ADC_CKPER
| CLK_CEC_LSE
| CLK_I2C12_HSI
| CLK_I2C35_HSI
| CLK_UART1_HSI
| CLK_UART24_HSI
| CLK_UART35_HSI
| CLK_UART6_HSI
| CLK_UART78_HSI
| CLK_SPDIF_PLL4P
| CLK_FDCAN_PLL4Q
| CLK_SAI1_PLL3Q
| CLK_SAI2_PLL3Q
| CLK_SAI3_PLL3Q
| CLK_SAI4_PLL3Q
| CLK_RNG1_LSI
| CLK_RNG2_LSI
| CLK_LPTIM1_PCLK1
| CLK_LPTIM23_PCLK3
| CLK_LPTIM45_LSE
| >;
|
| /* VCO = 1300.0 MHz => P = 650 (CPU) */
| pll1: st,pll@0 {
| cfg = < 2 80 0 0 0 PQR(1,0,0) >;
| frac = < 0x800 >;
| u-boot,dm-pre-reloc;
| };
|
| /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
| pll2: st,pll@1 {
| cfg = < 2 65 1 0 0 PQR(1,1,1) >;
| frac = < 0x1400 >;
| u-boot,dm-pre-reloc;
| };
|
| /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
| pll3: st,pll@2 {
| cfg = < 1 33 1 16 36 PQR(1,1,1) >;
| frac = < 0x1a04 >;
| u-boot,dm-pre-reloc;
| };
|
| /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
| pll4: st,pll@3 {
| cfg = < 3 98 5 7 7 PQR(1,1,1) >;
| u-boot,dm-pre-reloc;
| };
| };
|
| &sdmmc1 {
| u-boot,dm-spl;
| };
|
| &sdmmc1_b4_pins_a {
| u-boot,dm-spl;
| pins {
| u-boot,dm-spl;
| };
| };
|
| &uart4 {
| u-boot,dm-pre-reloc;
| };
|
| &uart4_pins_a {
| u-boot,dm-pre-reloc;
| pins1 {
| u-boot,dm-pre-reloc;
| };
| pins2 {
| u-boot,dm-pre-reloc;
| };
| };
|
| &usbotg_hs {
| u-boot,force-b-session-valid;
| hnp-srp-disable;
| };
|
| &v3v3 {
| regulator-always-on;
| };
|
|
