Binding for a ST pll clock driver.
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This binding uses the common clock binding[1].
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Base address is located to the parent node. See clock binding[2]
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
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Required properties:
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- compatible : shall be:
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"st,clkgen-pll0"
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"st,clkgen-pll1"
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"st,stih407-clkgen-plla9"
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"st,stih418-clkgen-plla9"
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- #clock-cells : From common clock binding; shall be set to 1.
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- clocks : From common clock binding
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- clock-output-names : From common clock binding.
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Example:
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0xffff>;
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-clkgen-plla9";
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clocks = <&clk_sysin>;
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clock-output-names = "clockgen-a9-pll-odf";
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};
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};
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