/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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#ifndef _MXS_SAIF_H
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#define _MXS_SAIF_H
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#define SAIF_CTRL 0x0
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#define SAIF_STAT 0x10
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#define SAIF_DATA 0x20
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#define SAIF_VERSION 0X30
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/* SAIF_CTRL */
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#define BM_SAIF_CTRL_SFTRST 0x80000000
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#define BM_SAIF_CTRL_CLKGATE 0x40000000
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#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27
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#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000
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#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
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(((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
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#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000
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#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000
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#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000
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#define BP_SAIF_CTRL_RSRVD2 21
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#define BM_SAIF_CTRL_RSRVD2 0x00E00000
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#define BP_SAIF_CTRL_DMAWAIT_COUNT 16
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#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000
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#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
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(((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
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#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
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#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
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#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
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(((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
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#define BM_SAIF_CTRL_LRCLK_PULSE 0x00002000
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#define BM_SAIF_CTRL_BIT_ORDER 0x00001000
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#define BM_SAIF_CTRL_DELAY 0x00000800
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#define BM_SAIF_CTRL_JUSTIFY 0x00000400
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#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200
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#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100
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#define BP_SAIF_CTRL_WORD_LENGTH 4
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#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0
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#define BF_SAIF_CTRL_WORD_LENGTH(v) \
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(((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
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#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008
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#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004
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#define BM_SAIF_CTRL_READ_MODE 0x00000002
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#define BM_SAIF_CTRL_RUN 0x00000001
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/* SAIF_STAT */
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#define BM_SAIF_STAT_PRESENT 0x80000000
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#define BP_SAIF_STAT_RSRVD2 17
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#define BM_SAIF_STAT_RSRVD2 0x7FFE0000
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#define BF_SAIF_STAT_RSRVD2(v) \
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(((v) << 17) & BM_SAIF_STAT_RSRVD2)
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#define BM_SAIF_STAT_DMA_PREQ 0x00010000
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#define BP_SAIF_STAT_RSRVD1 7
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#define BM_SAIF_STAT_RSRVD1 0x0000FF80
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#define BF_SAIF_STAT_RSRVD1(v) \
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(((v) << 7) & BM_SAIF_STAT_RSRVD1)
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#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
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#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020
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#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010
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#define BP_SAIF_STAT_RSRVD0 1
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#define BM_SAIF_STAT_RSRVD0 0x0000000E
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#define BF_SAIF_STAT_RSRVD0(v) \
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(((v) << 1) & BM_SAIF_STAT_RSRVD0)
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#define BM_SAIF_STAT_BUSY 0x00000001
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/* SAFI_DATA */
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#define BP_SAIF_DATA_PCM_RIGHT 16
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#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000
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#define BF_SAIF_DATA_PCM_RIGHT(v) \
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(((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
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#define BP_SAIF_DATA_PCM_LEFT 0
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#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF
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#define BF_SAIF_DATA_PCM_LEFT(v) \
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(((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
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/* SAIF_VERSION */
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#define BP_SAIF_VERSION_MAJOR 24
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#define BM_SAIF_VERSION_MAJOR 0xFF000000
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#define BF_SAIF_VERSION_MAJOR(v) \
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(((v) << 24) & BM_SAIF_VERSION_MAJOR)
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#define BP_SAIF_VERSION_MINOR 16
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#define BM_SAIF_VERSION_MINOR 0x00FF0000
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#define BF_SAIF_VERSION_MINOR(v) \
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(((v) << 16) & BM_SAIF_VERSION_MINOR)
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#define BP_SAIF_VERSION_STEP 0
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#define BM_SAIF_VERSION_STEP 0x0000FFFF
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#define BF_SAIF_VERSION_STEP(v) \
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(((v) << 0) & BM_SAIF_VERSION_STEP)
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#define MXS_SAIF_MCLK 0
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#include "mxs-pcm.h"
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struct mxs_saif {
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struct device *dev;
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struct clk *clk;
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unsigned int mclk;
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unsigned int mclk_in_use;
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void __iomem *base;
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unsigned int id;
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unsigned int master_id;
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unsigned int cur_rate;
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unsigned int ongoing;
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u32 fifo_underrun;
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u32 fifo_overrun;
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enum {
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MXS_SAIF_STATE_STOPPED,
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MXS_SAIF_STATE_RUNNING,
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} state;
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};
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extern int mxs_saif_put_mclk(unsigned int saif_id);
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extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
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unsigned int rate);
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#endif
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