// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
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*
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* Author: Damon Ding <damon.ding@rock-chips.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/time.h>
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#include "rkx110_x120.h"
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#include "rkx120_reg.h"
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/*
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* regs for pwm v1-v3
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*/
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#define PWM_CTRL_TIMER_EN (1 << 0)
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#define PWM_CTRL_OUTPUT_EN (1 << 3)
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#define PWM_ENABLE (1 << 0)
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#define PWM_MODE_SHIFT 1
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#define PWM_MODE_MASK (0x3 << PWM_MODE_SHIFT)
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#define PWM_ONESHOT (0 << PWM_MODE_SHIFT)
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#define PWM_CONTINUOUS (1 << PWM_MODE_SHIFT)
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#define PWM_CAPTURE (2 << PWM_MODE_SHIFT)
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#define PWM_DUTY_POSITIVE (1 << 3)
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#define PWM_DUTY_NEGATIVE (0 << 3)
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#define PWM_INACTIVE_NEGATIVE (0 << 4)
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#define PWM_INACTIVE_POSITIVE (1 << 4)
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#define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
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#define PWM_OUTPUT_LEFT (0 << 5)
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#define PWM_OUTPUT_CENTER (1 << 5)
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#define PWM_LOCK_EN (1 << 6)
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#define PWM_LP_DISABLE (0 << 8)
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#define PWM_CLK_SEL_SHIFT 9
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#define PWM_CLK_SEL_MASK (1 << PWM_CLK_SEL_SHIFT)
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#define PWM_SEL_NO_SCALED_CLOCK (0 << PWM_CLK_SEL_SHIFT)
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#define PWM_SEL_SCALED_CLOCK (1 << PWM_CLK_SEL_SHIFT)
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#define PWM_PRESCELE_SHIFT 12
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#define PWM_PRESCALE_MASK (0x3 << PWM_PRESCELE_SHIFT)
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#define PWM_SCALE_SHIFT 16
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#define PWM_SCALE_MASK (0xff << PWM_SCALE_SHIFT)
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#define PWM_ONESHOT_COUNT_SHIFT 24
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#define PWM_ONESHOT_COUNT_MASK (0xff << PWM_ONESHOT_COUNT_SHIFT)
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#define PWM_REG_INTSTS(n) ((3 - (n)) * 0x10 + 0x10)
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#define PWM_REG_INT_EN(n) ((3 - (n)) * 0x10 + 0x14)
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#define PWM_CH_INT(n) BIT(n)
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#define PWM_DCLK_RATE 24000000
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struct rkx120_pwm_chip {
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struct pwm_chip chip;
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struct rk_serdes *serdes;
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const struct rkx120_pwm_data *data;
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unsigned long clk_rate;
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bool center_aligned;
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bool oneshot_en;
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u32 remote_id;
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u32 channel_id;
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};
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struct rkx120_pwm_regs {
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unsigned long base;
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unsigned long duty;
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unsigned long period;
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unsigned long cntr;
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unsigned long ctrl;
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};
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struct rkx120_pwm_data {
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struct rkx120_pwm_regs regs;
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unsigned int prescaler;
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bool supports_polarity;
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bool supports_lock;
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u32 enable_conf;
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u32 enable_conf_mask;
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u32 oneshot_cnt_max;
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};
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static inline int rkx120_pwm_write(struct rk_serdes *serdes, u8 remote_id, u32 reg, u32 val)
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{
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struct i2c_client *client = serdes->chip[remote_id].client;
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return serdes->i2c_write_reg(client, reg, val);
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}
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static inline int rkx120_pwm_read(struct rk_serdes *serdes, u8 remote_id, u32 reg, u32 *val)
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{
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struct i2c_client *client = serdes->chip[remote_id].client;
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return serdes->i2c_read_reg(client, reg, val);
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}
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static inline struct rkx120_pwm_chip *to_rkx120_pwm_chip(struct pwm_chip *c)
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{
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return container_of(c, struct rkx120_pwm_chip, chip);
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}
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static void rkx120_pwm_get_state(struct pwm_chip *chip,
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struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct rkx120_pwm_chip *pc = to_rkx120_pwm_chip(chip);
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u32 enable_conf = pc->data->enable_conf;
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u64 tmp;
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u32 val;
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rkx120_pwm_read(pc->serdes, pc->remote_id, PWM_PERIOD_HPR(pc->channel_id), &val);
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tmp = val * pc->data->prescaler * NSEC_PER_SEC;
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state->period = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
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rkx120_pwm_read(pc->serdes, pc->remote_id, PWM_DUTY_LPR(pc->channel_id), &val);
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tmp = val * pc->data->prescaler * NSEC_PER_SEC;
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state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, pc->clk_rate);
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rkx120_pwm_read(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), &val);
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if (pc->oneshot_en)
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enable_conf &= ~PWM_CONTINUOUS;
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state->enabled = (val & enable_conf) == enable_conf;
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if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE))
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state->polarity = PWM_POLARITY_INVERSED;
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else
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state->polarity = PWM_POLARITY_NORMAL;
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}
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static void rkx120_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct rkx120_pwm_chip *pc = to_rkx120_pwm_chip(chip);
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unsigned long period, duty, delay_ns;
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u64 div;
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u32 ctrl;
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u8 dclk_div = 1;
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#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
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if (state->oneshot_count > 0 && state->oneshot_count <= pc->data->oneshot_cnt_max)
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dclk_div = 2;
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#endif
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/*
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* Since period and duty cycle registers have a width of 32
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* bits, every possible input period can be obtained using the
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* default prescaler value for all practical clock rate values.
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*/
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div = (u64)pc->clk_rate * state->period;
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period = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);
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div = (u64)pc->clk_rate * state->duty_cycle;
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duty = DIV_ROUND_CLOSEST_ULL(div, dclk_div * pc->data->prescaler * NSEC_PER_SEC);
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if (pc->data->supports_lock) {
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div = (u64)10 * NSEC_PER_SEC * dclk_div * pc->data->prescaler;
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delay_ns = DIV_ROUND_UP_ULL(div, pc->clk_rate);
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}
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/*
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* Lock the period and duty of previous configuration, then
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* change the duty and period, that would not be effective.
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*/
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rkx120_pwm_read(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), &ctrl);
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#ifdef CONFIG_PWM_ROCKCHIP_ONESHOT
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if (state->oneshot_count > 0 && state->oneshot_count <= pc->data->oneshot_cnt_max) {
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/*
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* This is a workaround, an uncertain waveform will be
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* generated after oneshot ends. It is needed to enable
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* the dclk scale function to resolve it. It doesn't
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* matter what the scale factor is, just make sure the
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* scale function is turned on, for which we set scale
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* factor to 2.
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*/
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ctrl &= ~PWM_SCALE_MASK;
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ctrl |= (dclk_div / 2) << PWM_SCALE_SHIFT;
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ctrl &= ~PWM_CLK_SEL_MASK;
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ctrl |= PWM_SEL_SCALED_CLOCK;
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pc->oneshot_en = true;
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ctrl &= ~PWM_MODE_MASK;
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ctrl |= PWM_ONESHOT;
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ctrl &= ~PWM_ONESHOT_COUNT_MASK;
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ctrl |= (state->oneshot_count - 1) << PWM_ONESHOT_COUNT_SHIFT;
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} else {
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ctrl &= ~PWM_SCALE_MASK;
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ctrl &= ~PWM_CLK_SEL_MASK;
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ctrl |= PWM_SEL_NO_SCALED_CLOCK;
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if (state->oneshot_count)
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dev_err(chip->dev, "Oneshot_count must be between 1 and %d.\n",
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pc->data->oneshot_cnt_max);
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pc->oneshot_en = false;
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ctrl &= ~PWM_MODE_MASK;
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ctrl |= PWM_CONTINUOUS;
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ctrl &= ~PWM_ONESHOT_COUNT_MASK;
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}
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#endif
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/*
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* Lock the period and duty of previous configuration, then
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* change the duty and period, that would not be effective.
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*/
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if (pc->data->supports_lock) {
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ctrl |= PWM_LOCK_EN;
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rkx120_pwm_write(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), ctrl);
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}
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rkx120_pwm_write(pc->serdes, pc->remote_id, PWM_PERIOD_HPR(pc->channel_id), period);
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rkx120_pwm_write(pc->serdes, pc->remote_id, PWM_DUTY_LPR(pc->channel_id), duty);
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if (pc->data->supports_polarity) {
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ctrl &= ~PWM_POLARITY_MASK;
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if (state->polarity == PWM_POLARITY_INVERSED)
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ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
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else
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ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
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}
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/*
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* Unlock and set polarity at the same time, the configuration of duty,
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* period and polarity would be effective together at next period. It
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* takes 10 dclk cycles to make sure lock works before unlocking.
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*/
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if (pc->data->supports_lock) {
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ctrl &= ~PWM_LOCK_EN;
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ndelay(delay_ns);
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}
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rkx120_pwm_write(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), ctrl);
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}
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static int rkx120_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm, bool enable)
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{
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struct rkx120_pwm_chip *pc = to_rkx120_pwm_chip(chip);
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u32 enable_conf = pc->data->enable_conf;
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u32 val;
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rkx120_pwm_read(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), &val);
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val &= ~pc->data->enable_conf_mask;
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if (pc->data->enable_conf_mask & PWM_OUTPUT_CENTER) {
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if (pc->center_aligned)
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val |= PWM_OUTPUT_CENTER;
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}
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if (enable) {
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val |= enable_conf;
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if (pc->oneshot_en)
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val &= ~PWM_CONTINUOUS;
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} else {
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val &= ~enable_conf;
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}
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rkx120_pwm_write(pc->serdes, pc->remote_id, PWM_CTRL(pc->channel_id), val);
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return 0;
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}
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static int rkx120_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct rkx120_pwm_chip *pc = to_rkx120_pwm_chip(chip);
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struct pwm_state curstate;
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bool enabled;
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int ret = 0;
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pwm_get_state(pwm, &curstate);
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enabled = curstate.enabled;
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if (state->polarity != curstate.polarity && enabled &&
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!pc->data->supports_lock) {
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ret = rkx120_pwm_enable(chip, pwm, false);
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if (ret)
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return ret;
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enabled = false;
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}
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rkx120_pwm_config(chip, pwm, state);
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if (state->enabled != enabled) {
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ret = rkx120_pwm_enable(chip, pwm, state->enabled);
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if (ret)
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return ret;
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}
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return ret;
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}
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static const struct pwm_ops rkx120_pwm_ops = {
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.get_state = rkx120_pwm_get_state,
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.apply = rkx120_pwm_apply,
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.owner = THIS_MODULE,
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};
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static const struct rkx120_pwm_data rkx120_pwm_data = {
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.prescaler = 1,
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.supports_polarity = true,
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.supports_lock = true,
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.enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
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PWM_CONTINUOUS,
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.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
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.oneshot_cnt_max = 0x100,
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};
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static const struct of_device_id rkx120_pwm_dt_ids[] = {
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{ .compatible = "rockchip,rkx120-pwm", .data = &rkx120_pwm_data},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, rkx120_pwm_dt_ids);
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static int rkx120_pwm_probe(struct platform_device *pdev)
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{
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struct rk_serdes *serdes = dev_get_drvdata(pdev->dev.parent);
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const struct of_device_id *id;
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struct rkx120_pwm_chip *pc;
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u32 remote_id, channel_id;
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int ret;
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id = of_match_device(rkx120_pwm_dt_ids, &pdev->dev);
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if (!id)
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return -EINVAL;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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platform_set_drvdata(pdev, pc);
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pc->data = id->data;
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &rkx120_pwm_ops;
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pc->chip.base = -1;
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pc->chip.npwm = 1;
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if (pc->data->supports_polarity) {
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pc->chip.of_xlate = of_pwm_xlate_with_flags;
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pc->chip.of_pwm_n_cells = 3;
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}
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pc->clk_rate = PWM_DCLK_RATE;
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pc->serdes = serdes;
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pc->center_aligned = device_property_read_bool(&pdev->dev, "center-aligned");
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ret = of_property_read_u32(pdev->dev.of_node, "channel-id", &channel_id);
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if (ret) {
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dev_err(&pdev->dev, "failed to read pwm channel id\n");
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return ret;
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}
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pc->channel_id = channel_id;
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ret = of_property_read_u32(pdev->dev.of_node, "remote-id", &remote_id);
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if (ret) {
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dev_err(&pdev->dev, "failed to read pwm remote id\n");
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return ret;
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}
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pc->remote_id = remote_id;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int rkx120_pwm_remove(struct platform_device *pdev)
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{
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struct rkx120_pwm_chip *pc = platform_get_drvdata(pdev);
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return pwmchip_remove(&pc->chip);
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}
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static struct platform_driver rkx120_pwm_driver = {
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.driver = {
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.name = "rkx120-pwm",
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.of_match_table = rkx120_pwm_dt_ids,
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},
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.probe = rkx120_pwm_probe,
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.remove = rkx120_pwm_remove,
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};
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module_platform_driver(rkx120_pwm_driver);
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