/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2023 Rockchip Electronics Co. Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _CRU_RKX111_H
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#include "cru_rkx110.h"
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// RXCRU_SOFTRST_CON02(Offset:0x408)
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#define RKX111_SRST_DRESETN_VICAP_CSI_LS 0x0000002E
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// RXCRU_SOFTRST_CON05(Offset:0x414)
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#define RKX111_SRST_RESETN_D_DSI_0_REC_RKLINK_TX 0x00000056
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#define RKX111_SRST_RESETN_D_DSI_1_REC_RKLINK_TX 0x00000057
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// RXCRU_SOFTRST_CON06(Offset:0x418)
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#define RKX111_SRST_RESETN_D_LVDS0_PATTERN_GEN 0x00000066
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#define RKX111_SRST_RESETN_D_LVDS1_PATTERN_GEN 0x00000067
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// RXCRU_SOFTRST_CON11(Offset:0x42C)
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#define RKX111_SRST_PRESETN_LBIST_ADA_RX 0x000000B1
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// RXCRU_GATE_CON02(Offset:0x308)
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#define RKX111_DCLK_RX_PRE_200M_GATE 0x0000002D
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#define RKX111_DCLK_VICAP_CSI_LS_GATE 0x0000002E
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// RXCRU_GATE_CON04(Offset:0x310)
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#define RKX111_CLK_D_DSI_0_RKLINK_TX_PRE_GATE 0x00000044
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#define RKX111_CLK_D_DSI_1_RKLINK_TX_PRE_GATE 0x00000045
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#define RKX111_CLK_D_LVDS0_RKLINK_TX_GATE 0x00000047
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#define RKX111_CLK_D_LVDS0_RKLINK_TX_PRE_GATE 0x00000048
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#define RKX111_CLK_D_LVDS1_RKLINK_TX_GATE 0x00000049
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#define RKX111_CLK_D_LVDS1_RKLINK_TX_PRE_GATE 0x0000004A
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#define RKX111_DCLK_D_DSI_0_REC_GATE 0x0000004D
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#define RKX111_DCLK_D_DSI_1_REC_GATE 0x0000004E
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// RXCRU_GATE_CON05(Offset:0x314)
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#define RKX111_DCLK_D_DSI_0_REC_RKLINK_TX_GATE 0x00000056
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#define RKX111_DCLK_D_DSI_1_REC_RKLINK_TX_GATE 0x00000057
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#define RKX111_CLK_D_DSI_0_RKLINK_TX_GATE 0x00000058
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#define RKX111_CLK_D_DSI_1_RKLINK_TX_GATE 0x00000059
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// RXCRU_GATE_CON06(Offset:0x318)
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_GATE 0x00000066
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_GATE 0x00000067
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// RXCRU_GATE_CON11(Offset:0x32C)
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#define RKX111_PCLK_LBIST_ADA_RX_GATE 0x000000B1
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// RXCRU_CLKSEL_CON05(Offset:0x114)
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#define RKX111_DCLK_D_DSI_0_REC_DIV 0x08000005
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#define RKX111_DCLK_D_DSI_0_REC_SEL 0x020E0005
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#define RKX111_DCLK_D_DSI_0_REC_SEL_CLK_RXPLL_MUX 0U
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#define RKX111_DCLK_D_DSI_0_REC_SEL_CLK_CPLL_MUX 1U
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#define RKX111_DCLK_D_DSI_0_REC_SEL_XIN_OSC0_FUNC 2U
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// RXCRU_CLKSEL_CON06(Offset:0x118)
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#define RKX111_DCLK_D_DSI_1_REC_DIV 0x08000006
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#define RKX111_DCLK_D_DSI_1_REC_SEL 0x020E0006
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#define RKX111_DCLK_D_DSI_1_REC_SEL_CLK_RXPLL_MUX 0U
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#define RKX111_DCLK_D_DSI_1_REC_SEL_CLK_CPLL_MUX 1U
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#define RKX111_DCLK_D_DSI_1_REC_SEL_XIN_OSC0_FUNC 2U
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// RXCRU_CLKSEL_CON13(Offset:0x134)
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_DIV 0x0800000D
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL 0x020E000D
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_CLK_RXPLL_MUX 0U
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_CLK_CPLL_MUX 1U
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#define RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL_XIN_OSC0_FUNC 2U
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// RXCRU_CLKSEL_CON14(Offset:0x138)
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_DIV 0x0800000E
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL 0x020E000E
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_CLK_RXPLL_MUX 0U
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_CLK_CPLL_MUX 1U
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#define RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL_XIN_OSC0_FUNC 2U
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// RXCRU_CLKSEL_CON16(Offset:0x140)
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#define RKX111_DCLK_RX_PRE_200M_DIV 0x06000010
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#define RKX111_DCLK_RX_PRE_200M_SEL 0x02060010
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#define RKX111_DCLK_RX_PRE_200M_SEL_CLK_RXPLL_MUX 0U
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#define RKX111_DCLK_RX_PRE_200M_SEL_CLK_CPLL_MUX 1U
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#define RKX111_DCLK_RX_PRE_200M_SEL_XIN_OSC0_FUNC 2U
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// RXCRU_CLKSEL_CON17(Offset:0x144)
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#define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL 0x010C0011
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#define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL_CLK_D_DSI_0_RKLINK_TX_PRE 0U
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#define RKX111_CLK_D_DSI_0_RKLINK_TX_SEL_CLK_D_DSI_0_PATTERN_GEN 1U
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#define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL 0x010D0011
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#define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL_CLK_D_DSI_1_RKLINK_TX_PRE 0U
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#define RKX111_CLK_D_DSI_1_RKLINK_TX_SEL_CLK_D_DSI_1_PATTERN_GEN 1U
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#define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL 0x010E0011
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#define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL_CLK_D_LVDS0_RKLINK_TX_PRE 0U
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#define RKX111_CLK_D_LVDS0_RKLINK_TX_SEL_CLK_D_LVDS0_PATTERN_GEN 1U
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#define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL 0x010F0011
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#define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL_CLK_D_LVDS1_RKLINK_TX_PRE 0U
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#define RKX111_CLK_D_LVDS1_RKLINK_TX_SEL_CLK_D_LVDS1_PATTERN_GEN 1U
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/* COMPOSITE */
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#define RKX111_CPS_DCLK_RX_PRE_200M COMPOSITE_CLK(RKX111_DCLK_RX_PRE_200M_SEL, RKX111_DCLK_RX_PRE_200M_DIV)
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/* lvds_pattern_gen => lvds_rklink */
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#define RKX111_CPS_CLK_D_LVDS0_PATTERN_GEN COMPOSITE_CLK(RKX111_CLK_D_LVDS0_PATTERN_GEN_SEL, RKX111_CLK_D_LVDS0_PATTERN_GEN_DIV)
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#define RKX111_CPS_CLK_D_LVDS1_PATTERN_GEN COMPOSITE_CLK(RKX111_CLK_D_LVDS1_PATTERN_GEN_SEL, RKX111_CLK_D_LVDS1_PATTERN_GEN_DIV)
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#define RKX111_CPS_CLK_D_LVDS0_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_LVDS0_RKLINK_TX_SEL, 0)
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#define RKX111_CPS_CLK_D_LVDS1_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_LVDS1_RKLINK_TX_SEL, 0)
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/* dsi_rec => dsi_rklink */
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#define RKX111_CPS_DCLK_D_DSI_0_REC COMPOSITE_CLK(RKX111_DCLK_D_DSI_0_REC_SEL, RKX111_DCLK_D_DSI_0_REC_DIV)
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#define RKX111_CPS_DCLK_D_DSI_1_REC COMPOSITE_CLK(RKX111_DCLK_D_DSI_1_REC_SEL, RKX111_DCLK_D_DSI_1_REC_DIV)
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#define RKX111_CPS_CLK_D_DSI_0_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_DSI_0_RKLINK_TX_SEL, 0)
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#define RKX111_CPS_CLK_D_DSI_1_RKLINK_TX COMPOSITE_CLK(RKX111_CLK_D_DSI_1_RKLINK_TX_SEL, 0)
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#endif
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