/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
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*
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _CRU_CORE_H_
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#define _CRU_CORE_H_
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#include "hal_def.h"
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#include "hal_os_def.h"
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#define DEBUG_CRU_INIT 0
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#define CRU_LOGLEVEL 3
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#define __cru_print(level, fmt, ...) \
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({ \
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level < CRU_LOGLEVEL ? HAL_SYSLOG("[HAL CRU] " fmt, ##__VA_ARGS__) : 0; \
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})
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#define CRU_ERR(fmt, ...) __cru_print(0, "ERROR: " fmt, ##__VA_ARGS__)
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#define CRU_WARN(fmt, ...) __cru_print(1, "WARN: " fmt, ##__VA_ARGS__)
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#define CRU_MSG(fmt, ...) __cru_print(2, fmt, ##__VA_ARGS__)
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#define CRU_DBG(fmt, ...) __cru_print(3, fmt, ##__VA_ARGS__) /* driver */
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#define CRU_DBGF(fmt, ...) __cru_print(4, fmt, ##__VA_ARGS__) /* core function */
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#define CRU_DBGR(fmt, ...) __cru_print(5, fmt, ##__VA_ARGS__) /* core register */
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#define HAL_ENABLE_SET_RATE_VERIFY 0
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#define _MHZ(n) ((n) * 1000000U)
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#define OSC_24M _MHZ(24)
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#define HAL_HWCLK_MAX_NUM 16
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#define PLL_MAX_NUM 2
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typedef enum {
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RKX110_CPLL = 0,
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RKX110_RXPLL,
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RKX120_CPLL = 0,
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RKX120_TXPLL,
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} HAL_PLLType;
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typedef enum {
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CLK_UNDEF,
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CLK_RKX110,
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CLK_RKX120,
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CLK_ALL,
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CLK_MAX,
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} HAL_ClockType;
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/*
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* hwclk flags
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*/
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#define CLK_FLG_SET_RATE_VERIFY (1 << 0) /* set and readback verify */
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struct hwclk;
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struct xferclk {
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HAL_ClockType type;
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u32 version;
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char *name; /* slave addr is expected */
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void *client;
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HAL_RegRead_t *read;
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HAL_RegWrite_t *write;
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};
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struct clkTable {
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uint8_t type;
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const char *name;
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uint32_t clk;
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const char * *parents;
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uint32_t numParents;
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const char *extParent;
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uint32_t (*getFreq)(struct hwclk *hw, uint32_t clockName);
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};
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struct clkOps {
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struct clkTable *clkTable;
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HAL_Status (*clkInit)(struct hwclk *hw, struct xferclk *xfer);
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HAL_Status (*clkInitTestout)(struct hwclk *hw, uint32_t clockName,
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uint32_t muxValue, uint32_t divValue);
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HAL_Status (*clkSetFreq)(struct hwclk *hw, uint32_t clockName, uint32_t rate);
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uint32_t (*clkGetFreq)(struct hwclk *hw, uint32_t clockName);
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};
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struct clkGate {
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uint8_t enable_count;
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};
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struct hwclk {
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char name[32];
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uint32_t flags;
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HAL_ClockType type;
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uint32_t pllRate[PLL_MAX_NUM];
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uint32_t cru_base;
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uint32_t gate_con0;
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uint32_t sel_con0;
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uint32_t softrst_con0;
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uint32_t gbl_srst_fst;
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struct xferclk xfer;
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struct clkOps *ops;
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struct clkGate *gate;
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uint32_t num_gate;
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HAL_Mutex lock;
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};
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#define MASK_TO_WE(msk) ((msk) << 16)
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#define VAL_MASK_WE(msk, val) ((MASK_TO_WE(msk)) | (val))
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#define WRITE_REG_MASK_WE(reg, msk, val) \
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WRITE_REG(reg, (VAL_MASK_WE(msk, val)))
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#define _GENMASK(h, l) (((~0UL) << (l)) & (~0UL >> (HAL_BITS_PER_LONG - 1 - (h))))
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#define _GENVAL(x, h, l) ((uint32_t)(((x) & _GENMASK(h, l)) >> (l)))
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#define _GENVAL_D16(x, h, l) ((uint32_t)(((x) & _GENMASK(h, l)) / 16))
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#define _GENVAL_D16_REM(x, h, l) ((uint32_t)(((x) & _GENMASK(h, l)) % 16))
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#define _WIDTH_TO_MASK(w) ((1 << (w)) - 1)
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/*
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* RESET/GATE fields:
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* [31:16]: reserved
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* [15:12]: bank
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* [11:0]: id
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*/
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#define CLK_RESET_GET_REG_OFFSET(x) _GENVAL_D16(x, 11, 0)
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#define CLK_RESET_GET_BITS_SHIFT(x) _GENVAL_D16_REM(x, 11, 0)
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#define CLK_RESET_GET_REG_BANK(x) _GENVAL(x, 15, 12)
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#define CLK_GATE_GET_REG_OFFSET(x) CLK_RESET_GET_REG_OFFSET(x)
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#define CLK_GATE_GET_BITS_SHIFT(x) CLK_RESET_GET_BITS_SHIFT(x)
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#define CLK_GATE_GET_REG_BANK(x) CLK_RESET_GET_REG_BANK(x)
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/*
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* MUX/DIV fields:
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* [31:24]: width
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* [23:16]: shift
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* [15:12]: reserved
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* [11:8]: bank
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* [7:0]: reg
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*/
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#define CLK_MUX_GET_REG_OFFSET(x) _GENVAL(x, 7, 0)
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#define CLK_MUX_GET_BANK(x) _GENVAL(x, 11, 8)
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#define CLK_MUX_GET_BITS_SHIFT(x) _GENVAL(x, 23, 16)
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#define CLK_MUX_GET_WIDTH(x) _GENVAL(x, 31, 24)
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#define CLK_MUX_GET_MASK(x) (_WIDTH_TO_MASK(CLK_MUX_GET_WIDTH(x)) << CLK_MUX_GET_BITS_SHIFT(x))
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#define CLK_DIV_GET_REG_OFFSET(x) CLK_MUX_GET_REG_OFFSET(x)
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#define CLK_DIV_GET_BANK(x) CLK_MUX_GET_BANK(x)
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#define CLK_DIV_GET_BITS_SHIFT(x) CLK_MUX_GET_BITS_SHIFT(x)
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#define CLK_DIV_GET_WIDTH(x) CLK_MUX_GET_WIDTH(x)
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#define CLK_DIV_GET_MASK(x) CLK_MUX_GET_MASK(x)
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#define CLK_DIV_GET_MAXDIV(x) ((1 << CLK_DIV_GET_WIDTH(x)) - 1)
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#define CLK_GET_MUX(v32) \
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((uint32_t)((v32) & 0x0F0F00FFU))
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#define CLK_GET_DIV(v32) \
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((uint32_t)((((v32) & 0x0000FF00U) >> 8) | \
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(((v32) & 0xF0F00000U) >> 4)))
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#define COMPOSITE_CLK(mux, div) \
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(((mux) & 0x0F0F00FFU) | (((div) & 0xFFU) << 8) | \
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(((div) & 0x0F0F0000U) << 4))
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#define PNAME(x) static const char *x[]
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typedef enum {
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DUMP_UNDEF,
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DUMP_INT,
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DUMP_EXT,
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} HAL_DumpType;
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#define CLK_DECLARE(_type, _name, _clk, _parents, _numParents, _extParent, _getFreq) \
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{ \
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.type = _type, \
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.name = _name, \
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.clk = _clk, \
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.parents = _parents, \
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.numParents = _numParents, \
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.extParent = _extParent, \
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.getFreq = _getFreq, \
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}
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#define CLK_DECLARE_INT(_name, _clk, _parents) \
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CLK_DECLARE(DUMP_INT, _name, _clk, _parents, HAL_ARRAY_SIZE(_parents), HAL_NULL, HAL_NULL)
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#define CLK_DECLARE_EXT_PARENT(_name, _clk, _extParent, _getFreq) \
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CLK_DECLARE(DUMP_EXT, _name, _clk, HAL_NULL, 0, _extParent, _getFreq)
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#define CLK_DECLARE_EXT(_name, _clk, _getFreq) \
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CLK_DECLARE_EXT_PARENT(_name, _clk, HAL_NULL, _getFreq)
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#define RK_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac) \
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{ \
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.rate = _rate##U, .fbDiv = _fbdiv, .postDiv1 = _postdiv1, \
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.refDiv = _refdiv, .postDiv2 = _postdiv2, .dsmpd = _dsmpd, \
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.frac = _frac, \
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}
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#define DIV_NO_REM(pFreq, freq, maxDiv) \
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((!((pFreq) % (freq))) && ((pFreq) / (freq) <= (maxDiv)))
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#define HAL_DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
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/***************************** Structure Definition **************************/
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struct PLL_CONFIG {
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uint32_t rate;
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union {
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struct {
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uint32_t fbDiv;
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uint32_t postDiv1;
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uint32_t refDiv;
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uint32_t postDiv2;
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uint32_t dsmpd;
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uint32_t frac;
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};
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};
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};
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typedef enum {
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PLL_CPLL,
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PLL_RXPLL,
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PLL_TXPLL,
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} eCRU_PLL;
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struct PLL_SETUP {
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eCRU_PLL id;
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uint32_t conOffset0;
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uint32_t conOffset1;
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uint32_t conOffset2;
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uint32_t conOffset3;
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uint32_t conOffset6;
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uint32_t modeOffset;
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uint32_t stat0;
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uint32_t modeShift;
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uint32_t lockShift;
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uint32_t modeMask;
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const struct PLL_CONFIG *rateTable;
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uint8_t minRefdiv;
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uint8_t maxRefdiv;
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uint32_t minVco;
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uint32_t maxVco;
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uint32_t minFout;
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uint32_t maxFout;
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uint8_t sscgEn;
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};
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typedef enum {
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GLB_SRST_FST = 0xfdb9,
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GLB_SRST_SND = 0xeca8,
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} eCRU_GlbSrstType;
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/***************************** Function Declare ******************************/
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uint32_t HAL_CRU_Read(struct hwclk *hw, uint32_t reg);
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uint32_t HAL_CRU_Write(struct hwclk *hw, uint32_t reg, uint32_t val);
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uint32_t HAL_CRU_WriteMask(struct hwclk *hw, uint32_t reg,
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uint32_t msk, uint32_t val);
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int HAL_CRU_FreqGetMux4(struct hwclk *hw,
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uint32_t freq, uint32_t freq0,
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uint32_t freq1, uint32_t freq2, uint32_t freq3);
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int HAL_CRU_FreqGetMux3(struct hwclk *hw,
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uint32_t freq, uint32_t freq0,
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uint32_t freq1, uint32_t freq2);
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int HAL_CRU_FreqGetMux2(struct hwclk *hw,
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uint32_t freq, uint32_t freq0, uint32_t freq1);
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uint32_t HAL_CRU_MuxGetFreq4(struct hwclk *hw, uint32_t muxName,
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uint32_t freq0, uint32_t freq1,
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uint32_t freq2, uint32_t freq3);
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uint32_t HAL_CRU_MuxGetFreq3(struct hwclk *hw, uint32_t muxName,
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uint32_t freq0, uint32_t freq1, uint32_t freq2);
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uint32_t HAL_CRU_MuxGetFreq2(struct hwclk *hw, uint32_t muxName,
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uint32_t freq0, uint32_t freq1);
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int HAL_CRU_RoundFreqGetMux4(struct hwclk *hw, uint32_t freq,
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uint32_t pFreq0, uint32_t pFreq1,
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uint32_t pFreq2, uint32_t pFreq3, uint32_t *pFreqOut);
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int HAL_CRU_RoundFreqGetMux3(struct hwclk *hw, uint32_t freq,
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uint32_t pFreq0, uint32_t pFreq1,
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uint32_t pFreq2, uint32_t *pFreqOut);
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int HAL_CRU_RoundFreqGetMux2(struct hwclk *hw, uint32_t freq,
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uint32_t pFreq0, uint32_t pFreq1, uint32_t *pFreqOut);
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/**
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* @brief Get pll freq.
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* @param pSetup: Contains PLL register parameters
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* @return pll rate.
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*/
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uint32_t HAL_CRU_GetPllFreq(struct hwclk *hw, struct PLL_SETUP *pSetup);
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/**
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* @brief Set pll freq.
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* @param pSetup: Contains PLL register parameters
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* @param rate: pll set
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_SetPllFreq(struct hwclk *hw, struct PLL_SETUP *pSetup, uint32_t rate);
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/**
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* @brief Set pll power up.
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* @param pSetup: Contains PLL register parameters
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_SetPllPowerUp(struct hwclk *hw, struct PLL_SETUP *pSetup);
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/**
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* @brief Set pll power down.
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* @param pSetup: Contains PLL register parameters
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_SetPllPowerDown(struct hwclk *hw, struct PLL_SETUP *pSetup);
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/**
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* @brief Check if clk is enabled
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* @param clk: clock to check
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* @return HAL_Check.
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*/
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HAL_Check HAL_CRU_ClkIsEnabled(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Enable clk
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* @param clk: clock to set
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_ClkEnable(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Disable clk
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* @param clk: clock to set
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_ClkDisable(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Check if clk is reset
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* @param clk: clock to check
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* @return HAL_Check.
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*/
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HAL_Check HAL_CRU_ClkIsReset(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Assert the reset to the clk
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* @param clk: clock to assert
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_ClkResetAssert(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Deassert the reset to the clk
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* @param clk: clock to deassert
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* @return HAL_Status.
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*/
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HAL_Status HAL_CRU_ClkResetDeassert(struct hwclk *hw, uint32_t clk);
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/**
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* @brief Set integer div
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* @param divName: div id(struct hwclk *hw, Contains div offset, shift, mask information)
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* @param divValue: div value
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* @return NONE
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*/
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HAL_Status HAL_CRU_ClkSetDiv(struct hwclk *hw, uint32_t divName, uint32_t divValue);
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/**
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* @brief Get integer div
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* @param divName: div id (struct hwclk *hw,, Contains div offset, shift, mask information)
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* @return div value
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*/
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uint32_t HAL_CRU_ClkGetDiv(struct hwclk *hw, uint32_t divName);
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/**
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* @brief Set mux
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* @param muxName: mux id (struct hwclk *hw,, Contains mux offset, shift, mask information)
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* @param muxValue: mux value
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* @return NONE
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*/
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HAL_Status HAL_CRU_ClkSetMux(struct hwclk *hw, uint32_t muxName, uint32_t muxValue);
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/**
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* @brief Get mux
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* @param muxName: mux id (struct hwclk *hw, Contains mux offset, shift, mask information)
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* @return mux value
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*/
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uint32_t HAL_CRU_ClkGetMux(struct hwclk *hw, uint32_t muxName);
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/**
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* @brief Get clk freq.
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* @param clockName: CLOCK_Name id.
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* @return rate.
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* @attention these APIs allow direct use in the HAL layer.
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*/
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uint32_t HAL_CRU_ClkGetFreq(struct hwclk *hw, uint32_t clockName);
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/**
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* @brief Set clk freq.
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* @param clockName: CLOCK_Name id.
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* @param rate: clk rate.
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* @return HAL_Status.
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* @attention these APIs allow direct use in the HAL layer.
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*/
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HAL_Status HAL_CRU_ClkSetFreq(struct hwclk *hw, uint32_t clockName, uint32_t rate);
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/**
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* @brief assert CRU global software reset.
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* @param type: global software reset type.
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* @return HAL_INVAL if the SoC does not support.
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*/
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HAL_Status HAL_CRU_SetGlbSrst(struct hwclk *hw, eCRU_GlbSrstType type);
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/**
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* @brief Set clk testout
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* @param clockName: CLOCK_Name id.
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* @param muxValue: mux value.
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* @param divValue: div value.
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* @return HAL_INVAL if the SoC does not support.
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*/
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HAL_Status HAL_CRU_ClkSetTestout(struct hwclk *hw, uint32_t clockName,
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uint32_t muxValue, uint32_t divValue);
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/**
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* @brief Dump all clock tree
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*/
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void HAL_CRU_ClkDumpTree(HAL_ClockType type);
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/**
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* @brief CRU init for chip
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* @return HAL_INVAL if the SoC does not support.
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*/
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HAL_Status HAL_CRU_Init(void);
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/**
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* @brief Register CRU
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* @param xfer: the data to register
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* @return hwclk descriptor.
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*/
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struct hwclk *HAL_CRU_Register(struct xferclk xfer);
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/**
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* @brief Get hwclk
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* @param client: the unit data to find hwclk
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* @return hwclk descriptor.
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*/
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struct hwclk *HAL_CRU_ClkGet(void *client);
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/************************** chip ops *************************************/
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extern struct clkOps rkx110_clk_ops;
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extern struct clkOps rkx120_clk_ops;
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extern struct clkOps rkx111_clk_ops;
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extern struct clkOps rkx121_clk_ops;
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#endif
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