/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* STMicroelectronics st_lsm6dsr sensor driver
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*
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* Copyright 2020 STMicroelectronics Inc.
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*
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* Lorenzo Bianconi <lorenzo.bianconi@st.com>
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*/
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#ifndef ST_LSM6DSR_H
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#define ST_LSM6DSR_H
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#include <linux/device.h>
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#include <linux/iio/iio.h>
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#include <linux/delay.h>
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#define ST_LSM6DSR_MAX_ODR 833
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#define ST_LSM6DSR_ODR_LIST_SIZE 8
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#define ST_LSM6DSR_ODR_EXPAND(odr, uodr) ((odr * 1000000) + uodr)
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#define ST_LSM6DSR_DEV_NAME "lsm6dsr"
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#define ST_LSM6DSR_REG_FUNC_CFG_ACCESS_ADDR 0x01
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#define ST_LSM6DSR_REG_SHUB_REG_MASK BIT(6)
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#define ST_LSM6DSR_REG_FUNC_CFG_MASK BIT(7)
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#define ST_LSM6DSR_REG_FIFO_CTRL1_ADDR 0x07
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#define ST_LSM6DSR_REG_FIFO_CTRL2_ADDR 0x08
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#define ST_LSM6DSR_REG_FIFO_WTM_MASK GENMASK(8, 0)
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#define ST_LSM6DSR_REG_FIFO_WTM8_MASK BIT(0)
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#define ST_LSM6DSR_REG_FIFO_CTRL3_ADDR 0x09
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#define ST_LSM6DSR_REG_BDR_XL_MASK GENMASK(3, 0)
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#define ST_LSM6DSR_REG_BDR_GY_MASK GENMASK(7, 4)
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#define ST_LSM6DSR_REG_FIFO_CTRL4_ADDR 0x0a
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#define ST_LSM6DSR_REG_FIFO_MODE_MASK GENMASK(2, 0)
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#define ST_LSM6DSR_REG_ODR_T_BATCH_MASK GENMASK(5, 4)
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#define ST_LSM6DSR_REG_DEC_TS_MASK GENMASK(7, 6)
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#define ST_LSM6DSR_REG_INT1_CTRL_ADDR 0x0d
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#define ST_LSM6DSR_REG_INT2_CTRL_ADDR 0x0e
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#define ST_LSM6DSR_REG_INT_FIFO_TH_MASK BIT(3)
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#define ST_LSM6DSR_REG_WHOAMI_ADDR 0x0f
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#define ST_LSM6DSR_WHOAMI_VAL 0x6b
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#define ST_LSM6DSR_CTRL1_XL_ADDR 0x10
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#define ST_LSM6DSR_CTRL2_G_ADDR 0x11
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#define ST_LSM6DSR_REG_CTRL3_C_ADDR 0x12
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#define ST_LSM6DSR_REG_SW_RESET_MASK BIT(0)
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#define ST_LSM6DSR_REG_PP_OD_MASK BIT(4)
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#define ST_LSM6DSR_REG_H_LACTIVE_MASK BIT(5)
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#define ST_LSM6DSR_REG_BDU_MASK BIT(6)
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#define ST_LSM6DSR_REG_BOOT_MASK BIT(7)
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#define ST_LSM6DSR_REG_CTRL4_C_ADDR 0x13
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#define ST_LSM6DSR_REG_DRDY_MASK BIT(3)
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#define ST_LSM6DSR_REG_CTRL5_C_ADDR 0x14
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#define ST_LSM6DSR_REG_ROUNDING_MASK GENMASK(6, 5)
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#define ST_LSM6DSR_REG_CTRL9_XL_ADDR 0x18
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#define ST_LSM6DSR_REG_I3C_DISABLE_MASK BIT(1)
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#define ST_LSM6DSR_REG_CTRL10_C_ADDR 0x19
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#define ST_LSM6DSR_REG_TIMESTAMP_EN_MASK BIT(5)
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#define ST_LSM6DSR_REG_OUT_TEMP_L_ADDR 0x20
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#define ST_LSM6DSR_REG_OUTX_L_G_ADDR 0x22
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#define ST_LSM6DSR_REG_OUTY_L_G_ADDR 0x24
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#define ST_LSM6DSR_REG_OUTZ_L_G_ADDR 0x26
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#define ST_LSM6DSR_REG_OUTX_L_A_ADDR 0x28
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#define ST_LSM6DSR_REG_OUTY_L_A_ADDR 0x2a
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#define ST_LSM6DSR_REG_OUTZ_L_A_ADDR 0x2c
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#define ST_LSM6DSR_REG_FIFO_STATUS1_ADDR 0x3a
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#define ST_LSM6DSR_REG_FIFO_STATUS_DIFF GENMASK(9, 0)
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#define ST_LSM6DSR_REG_TIMESTAMP0_ADDR 0x40
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#define ST_LSM6DSR_REG_TIMESTAMP2_ADDR 0x42
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#define ST_LSM6DSR_REG_TAP_CFG0_ADDR 0x56
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#define ST_LSM6DSR_REG_TAP_X_EN_MASK BIT(3)
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#define ST_LSM6DSR_REG_TAP_Y_EN_MASK BIT(2)
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#define ST_LSM6DSR_REG_TAP_Z_EN_MASK BIT(1)
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#define ST_LSM6DSR_REG_LIR_MASK BIT(0)
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#define ST_LSM6DSR_REG_MD1_CFG_ADDR 0x5e
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#define ST_LSM6DSR_REG_MD2_CFG_ADDR 0x5f
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#define ST_LSM6DSR_REG_INT2_TIMESTAMP_MASK BIT(0)
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#define ST_LSM6DSR_REG_INT_EMB_FUNC_MASK BIT(1)
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#define ST_LSM6DSR_INTERNAL_FREQ_FINE 0x63
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#define ST_LSM6DSR_REG_FIFO_DATA_OUT_TAG_ADDR 0x78
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/* embedded registers */
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#define ST_LSM6DSR_REG_EMB_FUNC_INT1_ADDR 0x0a
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#define ST_LSM6DSR_REG_EMB_FUNC_INT2_ADDR 0x0e
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/* Timestamp Tick 25us/LSB */
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#define ST_LSM6DSR_TS_DELTA_NS 25000ULL
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#define ST_LSM6DSR_TEMP_GAIN 256
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#define ST_LSM6DSR_TEMP_FS_GAIN (1000000 / ST_LSM6DSR_TEMP_GAIN)
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#define ST_LSM6DSR_TEMP_OFFSET 6400
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#define ST_LSM6DSR_SAMPLE_SIZE 6
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#define ST_LSM6DSR_TS_SAMPLE_SIZE 4
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#define ST_LSM6DSR_TAG_SIZE 1
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#define ST_LSM6DSR_FIFO_SAMPLE_SIZE (ST_LSM6DSR_SAMPLE_SIZE + \
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ST_LSM6DSR_TAG_SIZE)
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#define ST_LSM6DSR_MAX_FIFO_DEPTH 416
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#define ST_LSM6DSR_DATA_CHANNEL(chan_type, addr, mod, ch2, scan_idx, \
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rb, sb, sg) \
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{ \
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.type = chan_type, \
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.address = addr, \
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.modified = mod, \
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.channel2 = ch2, \
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
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BIT(IIO_CHAN_INFO_SCALE), \
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.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
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.scan_index = scan_idx, \
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.scan_type = { \
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.sign = sg, \
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.realbits = rb, \
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.storagebits = sb, \
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.endianness = IIO_LE, \
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}, \
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}
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static const struct iio_event_spec st_lsm6dsr_flush_event = {
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#ifdef CONFIG_NO_GKI
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.type = IIO_EV_TYPE_FIFO_FLUSH,
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.dir = IIO_EV_DIR_EITHER,
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#endif
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};
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static const struct iio_event_spec st_lsm6dsr_thr_event = {
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.type = IIO_EV_TYPE_THRESH,
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.dir = IIO_EV_DIR_RISING,
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.mask_separate = BIT(IIO_EV_INFO_ENABLE),
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};
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#define ST_LSM6DSR_EVENT_CHANNEL(ctype, etype) \
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{ \
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.type = ctype, \
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.modified = 0, \
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.scan_index = -1, \
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.indexed = -1, \
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.event_spec = &st_lsm6dsr_##etype##_event, \
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.num_event_specs = 1, \
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}
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#define ST_LSM6DSR_RX_MAX_LENGTH 64
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#define ST_LSM6DSR_TX_MAX_LENGTH 16
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/**
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* @struct st_lsm6dsr_transfer_buffer
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* @brief Buffer support for data transfer
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*
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* rx_buf: Data receive buffer.
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* tx_buf: Data transmit buffer.
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*/
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struct st_lsm6dsr_transfer_buffer {
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u8 rx_buf[ST_LSM6DSR_RX_MAX_LENGTH];
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u8 tx_buf[ST_LSM6DSR_TX_MAX_LENGTH] ____cacheline_aligned;
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};
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/**
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* @struct st_lsm6dsr_transfer_function
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* @brief Bus Transfer Function
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*
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* read: Bus read function to get register value from sensor.
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* write: Bus write function to set register value to sensor.
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*/
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struct st_lsm6dsr_transfer_function {
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int (*read)(struct device *dev, u8 addr, int len, u8 *data);
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int (*write)(struct device *dev, u8 addr, int len, const u8 *data);
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};
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/**
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* @struct st_lsm6dsr_reg
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* @brief Generic sensor register description
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*
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* addr: Register arress value.
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* mask: Register bitmask.
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*/
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struct st_lsm6dsr_reg {
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u8 addr;
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u8 mask;
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};
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enum st_lsm6dsr_suspend_resume_register {
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ST_LSM6DSR_CTRL1_XL_REG = 0,
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ST_LSM6DSR_CTRL2_G_REG,
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ST_LSM6DSR_REG_CTRL3_C_REG,
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ST_LSM6DSR_REG_CTRL4_C_REG,
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ST_LSM6DSR_REG_CTRL5_C_REG,
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ST_LSM6DSR_REG_CTRL10_C_REG,
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ST_LSM6DSR_REG_TAP_CFG0_REG,
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ST_LSM6DSR_REG_INT1_CTRL_REG,
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ST_LSM6DSR_REG_INT2_CTRL_REG,
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ST_LSM6DSR_REG_FIFO_CTRL1_REG,
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ST_LSM6DSR_REG_FIFO_CTRL2_REG,
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ST_LSM6DSR_REG_FIFO_CTRL3_REG,
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ST_LSM6DSR_REG_FIFO_CTRL4_REG,
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ST_LSM6DSR_SUSPEND_RESUME_REGS,
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};
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struct st_lsm6dsr_suspend_resume_entry {
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u8 addr;
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u8 val;
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u8 mask;
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};
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/**
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* @struct st_lsm6dsr_odr
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* @brief ODR sensor table entry
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*
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* In the ODR table the possible ODR supported by sensor can be defined in the
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* following format:
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* .odr_avl[0] = { 0, 0, 0x00 },
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* .odr_avl[1] = { 12, 500000, 0x01 }, ..... it means 12.5 Hz
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* .odr_avl[2] = { 26, 0, 0x02 }, ..... it means 26.0 Hz
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*
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* hz: Most significant part of ODR value (in Hz).
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* uhz: Least significant part of ODR value (in micro Hz).
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* val: Register value tu set ODR.
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*/
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struct st_lsm6dsr_odr {
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int hz;
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int uhz;
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u8 val;
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};
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/**
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* @struct st_lsm6dsr_odr_table_entry
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* @brief ODR sensor table
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*
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* odr_size: ODR table size.
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* reg: Sensor register description for ODR (address and mask).
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* odr_avl: All supported ODR values.
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*/
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struct st_lsm6dsr_odr_table_entry {
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u8 odr_size;
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struct st_lsm6dsr_reg reg;
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struct st_lsm6dsr_odr odr_avl[ST_LSM6DSR_ODR_LIST_SIZE];
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};
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/**
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* @struct st_lsm6dsr_fs
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* @brief Full scale entry
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*
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* reg: Sensor register description for FS (address and mask).
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* gain: The gain to obtain data value from raw data (LSB).
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* val: Register value.
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*/
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struct st_lsm6dsr_fs {
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struct st_lsm6dsr_reg reg;
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u32 gain;
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u8 val;
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};
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/**
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* @struct st_lsm6dsr_fs_table_entry
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* @brief Full scale table
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*
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* size: Full scale number of entry.
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* fs_avl: Full scale entry.
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*/
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#define ST_LSM6DSR_FS_LIST_SIZE 5
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#define ST_LSM6DSR_FS_ACC_LIST_SIZE 4
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#define ST_LSM6DSR_FS_GYRO_LIST_SIZE 5
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#define ST_LSM6DSR_FS_TEMP_LIST_SIZE 1
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struct st_lsm6dsr_fs_table_entry {
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u8 size;
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struct st_lsm6dsr_fs fs_avl[ST_LSM6DSR_FS_LIST_SIZE];
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};
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#define ST_LSM6DSR_ACC_FS_2G_GAIN IIO_G_TO_M_S_2(61)//
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#define ST_LSM6DSR_ACC_FS_4G_GAIN IIO_G_TO_M_S_2(61)//(122)
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#define ST_LSM6DSR_ACC_FS_8G_GAIN IIO_G_TO_M_S_2(61)//(244)
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#define ST_LSM6DSR_ACC_FS_16G_GAIN IIO_G_TO_M_S_2(61)//(488)
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#define ST_LSM6DSR_GYRO_FS_250_GAIN IIO_DEGREE_TO_RAD(8750)//
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#define ST_LSM6DSR_GYRO_FS_500_GAIN IIO_DEGREE_TO_RAD(8750)//(17500)
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#define ST_LSM6DSR_GYRO_FS_1000_GAIN IIO_DEGREE_TO_RAD(8750)//(35000)
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#define ST_LSM6DSR_GYRO_FS_2000_GAIN IIO_DEGREE_TO_RAD(8750)//(70000)
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#define ST_LSM6DSR_GYRO_FS_4000_GAIN IIO_DEGREE_TO_RAD(8750)//(140000)
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struct st_lsm6dsr_ext_dev_info {
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const struct st_lsm6dsr_ext_dev_settings *ext_dev_settings;
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u8 ext_dev_i2c_addr;
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};
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/**
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* @enum st_lsm6dsr_sensor_id
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* @brief Sensor Identifier
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*/
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enum st_lsm6dsr_sensor_id {
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ST_LSM6DSR_ID_GYRO,
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ST_LSM6DSR_ID_ACC,
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ST_LSM6DSR_ID_TEMP,
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ST_LSM6DSR_ID_EXT0,
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ST_LSM6DSR_ID_EXT1,
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ST_LSM6DSR_ID_STEP_COUNTER,
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ST_LSM6DSR_ID_STEP_DETECTOR,
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ST_LSM6DSR_ID_SIGN_MOTION,
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ST_LSM6DSR_ID_GLANCE,
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ST_LSM6DSR_ID_MOTION,
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ST_LSM6DSR_ID_NO_MOTION,
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ST_LSM6DSR_ID_WAKEUP,
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ST_LSM6DSR_ID_PICKUP,
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ST_LSM6DSR_ID_ORIENTATION,
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ST_LSM6DSR_ID_WRIST_TILT,
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ST_LSM6DSR_ID_TILT,
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ST_LSM6DSR_ID_MAX,
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};
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/**
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* @enum st_lsm6dsr_sensor_id
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* @brief Sensor Table Identifier
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*/
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static const enum st_lsm6dsr_sensor_id st_lsm6dsr_main_sensor_list[] = {
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[0] = ST_LSM6DSR_ID_GYRO,
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[1] = ST_LSM6DSR_ID_ACC,
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[2] = ST_LSM6DSR_ID_TEMP,
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[3] = ST_LSM6DSR_ID_STEP_COUNTER,
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[4] = ST_LSM6DSR_ID_STEP_DETECTOR,
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[5] = ST_LSM6DSR_ID_SIGN_MOTION,
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[6] = ST_LSM6DSR_ID_GLANCE,
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[7] = ST_LSM6DSR_ID_MOTION,
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[8] = ST_LSM6DSR_ID_NO_MOTION,
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[9] = ST_LSM6DSR_ID_WAKEUP,
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[10] = ST_LSM6DSR_ID_PICKUP,
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[11] = ST_LSM6DSR_ID_ORIENTATION,
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[12] = ST_LSM6DSR_ID_WRIST_TILT,
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[13] = ST_LSM6DSR_ID_TILT,
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};
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/**
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* @enum st_lsm6dsr_fifo_mode
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* @brief FIFO Modes
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*/
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enum st_lsm6dsr_fifo_mode {
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ST_LSM6DSR_FIFO_BYPASS = 0x0,
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ST_LSM6DSR_FIFO_CONT = 0x6,
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};
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/**
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* @enum st_lsm6dsr_fifo_mode - FIFO Buffer Status
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*/
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enum st_lsm6dsr_fifo_status {
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ST_LSM6DSR_HW_FLUSH,
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ST_LSM6DSR_HW_OPERATIONAL,
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};
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/**
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* @struct st_lsm6dsr_sensor
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* @brief ST IMU sensor instance
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*
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* id: Sensor identifier
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* hw: Pointer to instance of struct st_lsm6dsr_hw
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* ext_dev_info: Sensor hub i2c slave settings.
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* trig: Sensor iio trigger.
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* gain: Configured sensor sensitivity
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* odr: Output data rate of the sensor [Hz]
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* uodr: Output data rate of the sensor [uHz]
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* offset: Sensor data offset
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* decimator: Sensor decimator
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* dec_counter: Sensor decimator counter
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* old_data: Saved sensor data
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* max_watermark: Max supported watermark level
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* watermark: Sensor watermark level
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* batch_reg: Sensor reg/mask for FIFO batching register
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* last_fifo_timestamp: Store last sample timestamp in FIFO, used by flush
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*/
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struct st_lsm6dsr_sensor {
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enum st_lsm6dsr_sensor_id id;
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struct st_lsm6dsr_hw *hw;
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struct st_lsm6dsr_ext_dev_info ext_dev_info;
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struct iio_trigger *trig;
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u32 gain;
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int odr;
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int uodr;
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u32 offset;
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u8 decimator;
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u8 dec_counter;
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u16 max_watermark;
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u16 watermark;
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struct st_lsm6dsr_reg batch_reg;
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s64 last_fifo_timestamp;
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};
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/**
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* @struct st_lsm6dsr_hw
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* @brief ST IMU MEMS hw instance
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*
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* dev: Pointer to instance of struct device (I2C or SPI).
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* irq: Device interrupt line (I2C or SPI).
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* lock: Mutex to protect read and write operations.
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* fifo_lock: Mutex to prevent concurrent access to the hw FIFO.
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* page_lock: Mutex to prevent concurrent memory page configuration.
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* fifo_mode: FIFO operating mode supported by the device.
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* state: hw operational state.
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* enable_mask: Enabled sensor bitmask.
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* fsm_enable_mask: FSM Enabled sensor bitmask.
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* embfunc_pg0_irq_reg: Embedded function irq configuration register (page 0).
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* embfunc_irq_reg: Embedded function irq configuration register (other).
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* ext_data_len: Number of i2c slave devices connected to I2C master.
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* odr: Timestamp sample ODR [Hz]
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* uodr: Timestamp sample ODR [uHz]
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* ts_offset: Hw timestamp offset.
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* hw_ts: Latest hw timestamp from the sensor.
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* hw_ts_high: Manage timestamp rollover
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* tsample:
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* hw_ts_old:
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* delta_ts: Delta time between two consecutive interrupts.
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* delta_hw_ts:
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* ts: Latest timestamp from irq handler.
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* iio_devs: Pointers to acc/gyro iio_dev instances.
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* tf: Transfer function structure used by I/O operations.
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* tb: Transfer buffers used by SPI I/O operations.
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*/
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struct st_lsm6dsr_hw {
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struct device *dev;
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int irq;
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struct mutex lock;
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struct mutex fifo_lock;
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struct mutex page_lock;
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enum st_lsm6dsr_fifo_mode fifo_mode;
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unsigned long state;
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u32 enable_mask;
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u32 requested_mask;
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u32 suspend_mask;
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u16 fsm_enable_mask;
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u8 embfunc_irq_reg;
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u8 embfunc_pg0_irq_reg;
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u8 ext_data_len;
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int odr;
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int uodr;
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s64 ts_offset;
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u64 ts_delta_ns;
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s64 hw_ts;
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u32 val_ts_old;
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u32 hw_ts_high;
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s64 tsample;
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s64 delta_ts;
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s64 ts;
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struct iio_dev *iio_devs[ST_LSM6DSR_ID_MAX];
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const struct st_lsm6dsr_transfer_function *tf;
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struct st_lsm6dsr_transfer_buffer tb;
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};
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/**
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* @struct dev_pm_ops
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* @brief Power management callback function structure
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*/
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extern const struct dev_pm_ops st_lsm6dsr_pm_ops;
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static inline int st_lsm6dsr_read_atomic(struct st_lsm6dsr_hw *hw, u8 addr,
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int len, u8 *data)
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{
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int err;
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mutex_lock(&hw->page_lock);
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err = hw->tf->read(hw->dev, addr, len, data);
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mutex_unlock(&hw->page_lock);
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return err;
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}
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static inline int st_lsm6dsr_write_atomic(struct st_lsm6dsr_hw *hw, u8 addr,
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int len, u8 *data)
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{
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int err;
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mutex_lock(&hw->page_lock);
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err = hw->tf->write(hw->dev, addr, len, data);
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mutex_unlock(&hw->page_lock);
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return err;
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}
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int __st_lsm6dsr_write_with_mask(struct st_lsm6dsr_hw *hw, u8 addr, u8 mask,
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u8 val);
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static inline int st_lsm6dsr_write_with_mask(struct st_lsm6dsr_hw *hw, u8 addr,
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u8 mask, u8 val)
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{
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int err;
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mutex_lock(&hw->page_lock);
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err = __st_lsm6dsr_write_with_mask(hw, addr, mask, val);
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mutex_unlock(&hw->page_lock);
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return err;
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}
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static inline int st_lsm6dsr_set_page_access(struct st_lsm6dsr_hw *hw,
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u8 mask, u8 data)
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{
|
int err;
|
|
err = __st_lsm6dsr_write_with_mask(hw,
|
ST_LSM6DSR_REG_FUNC_CFG_ACCESS_ADDR,
|
mask, data);
|
usleep_range(100, 150);
|
|
return err;
|
}
|
|
static inline bool st_lsm6dsr_is_fifo_enabled(struct st_lsm6dsr_hw *hw)
|
{
|
return hw->enable_mask & (BIT(ST_LSM6DSR_ID_STEP_COUNTER) |
|
BIT(ST_LSM6DSR_ID_GYRO) |
|
BIT(ST_LSM6DSR_ID_ACC) |
|
BIT(ST_LSM6DSR_ID_EXT0) |
|
BIT(ST_LSM6DSR_ID_EXT1));
|
}
|
|
int st_lsm6dsr_probe(struct device *dev, int irq,
|
const struct st_lsm6dsr_transfer_function *tf_ops);
|
int st_lsm6dsr_remove(struct device *dev);
|
int st_lsm6dsr_shub_set_enable(struct st_lsm6dsr_sensor *sensor, bool enable);
|
int st_lsm6dsr_shub_probe(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_sensor_set_enable(struct st_lsm6dsr_sensor *sensor,
|
bool enable);
|
int st_lsm6dsr_irq_setup(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_buffers_setup(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_deallocate_buffers(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_get_odr_val(enum st_lsm6dsr_sensor_id id, int odr, int uodr,
|
int *podr, int *puodr, u8 *val);
|
int st_lsm6dsr_update_watermark(struct st_lsm6dsr_sensor *sensor,
|
u16 watermark);
|
ssize_t st_lsm6dsr_flush_fifo(struct device *dev,
|
struct device_attribute *attr,
|
const char *buf, size_t size);
|
ssize_t st_lsm6dsr_get_max_watermark(struct device *dev,
|
struct device_attribute *attr,
|
char *buf);
|
ssize_t st_lsm6dsr_get_watermark(struct device *dev,
|
struct device_attribute *attr,
|
char *buf);
|
ssize_t st_lsm6dsr_set_watermark(struct device *dev,
|
struct device_attribute *attr,
|
const char *buf, size_t size);
|
int st_lsm6dsr_set_page_access(struct st_lsm6dsr_hw *hw, u8 mask, u8 data);
|
int st_lsm6dsr_suspend_fifo(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_set_fifo_mode(struct st_lsm6dsr_hw *hw,
|
enum st_lsm6dsr_fifo_mode fifo_mode);
|
int __st_lsm6dsr_set_sensor_batching_odr(struct st_lsm6dsr_sensor *sensor,
|
bool enable);
|
int st_lsm6dsr_fsm_init(struct st_lsm6dsr_hw *hw);
|
int st_lsm6dsr_fsm_get_orientation(struct st_lsm6dsr_hw *hw, u8 *data);
|
int st_lsm6dsr_embfunc_sensor_set_enable(struct st_lsm6dsr_sensor *sensor,
|
bool enable);
|
int st_lsm6dsr_step_counter_set_enable(struct st_lsm6dsr_sensor *sensor,
|
bool enable);
|
int st_lsm6dsr_reset_step_counter(struct iio_dev *iio_dev);
|
int st_lsm6dsr_update_batching(struct iio_dev *iio_dev, bool enable);
|
int st_lsm6dsr_reset_hwts(struct st_lsm6dsr_hw *hw);
|
#endif /* ST_LSM6DSR_H */
|
