/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2015-2018 Etnaviv Project
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*/
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#ifndef __ETNAVIV_MMU_H__
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#define __ETNAVIV_MMU_H__
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#define ETNAVIV_PROT_READ (1 << 0)
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#define ETNAVIV_PROT_WRITE (1 << 1)
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enum etnaviv_iommu_version {
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ETNAVIV_IOMMU_V1 = 0,
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ETNAVIV_IOMMU_V2,
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};
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struct etnaviv_gpu;
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struct etnaviv_vram_mapping;
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struct etnaviv_iommu_global;
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struct etnaviv_iommu_context;
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struct etnaviv_iommu_ops {
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struct etnaviv_iommu_context *(*init)(struct etnaviv_iommu_global *);
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void (*free)(struct etnaviv_iommu_context *);
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int (*map)(struct etnaviv_iommu_context *context, unsigned long iova,
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phys_addr_t paddr, size_t size, int prot);
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size_t (*unmap)(struct etnaviv_iommu_context *context, unsigned long iova,
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size_t size);
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size_t (*dump_size)(struct etnaviv_iommu_context *);
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void (*dump)(struct etnaviv_iommu_context *, void *);
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void (*restore)(struct etnaviv_gpu *, struct etnaviv_iommu_context *);
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};
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extern const struct etnaviv_iommu_ops etnaviv_iommuv1_ops;
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extern const struct etnaviv_iommu_ops etnaviv_iommuv2_ops;
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#define ETNAVIV_PTA_SIZE SZ_4K
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#define ETNAVIV_PTA_ENTRIES (ETNAVIV_PTA_SIZE / sizeof(u64))
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struct etnaviv_iommu_global {
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struct device *dev;
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enum etnaviv_iommu_version version;
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const struct etnaviv_iommu_ops *ops;
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unsigned int use;
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struct mutex lock;
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void *bad_page_cpu;
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dma_addr_t bad_page_dma;
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u32 memory_base;
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/*
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* This union holds members needed by either MMUv1 or MMUv2, which
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* can not exist at the same time.
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*/
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union {
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struct {
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struct etnaviv_iommu_context *shared_context;
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} v1;
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struct {
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/* P(age) T(able) A(rray) */
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u64 *pta_cpu;
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dma_addr_t pta_dma;
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struct spinlock pta_lock;
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DECLARE_BITMAP(pta_alloc, ETNAVIV_PTA_ENTRIES);
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} v2;
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};
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};
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struct etnaviv_iommu_context {
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struct kref refcount;
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struct etnaviv_iommu_global *global;
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/* memory manager for GPU address area */
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struct mutex lock;
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struct list_head mappings;
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struct drm_mm mm;
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unsigned int flush_seq;
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/* Not part of the context, but needs to have the same lifetime */
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struct etnaviv_vram_mapping cmdbuf_mapping;
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};
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int etnaviv_iommu_global_init(struct etnaviv_gpu *gpu);
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void etnaviv_iommu_global_fini(struct etnaviv_gpu *gpu);
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struct etnaviv_gem_object;
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int etnaviv_iommu_map_gem(struct etnaviv_iommu_context *context,
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struct etnaviv_gem_object *etnaviv_obj, u32 memory_base,
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struct etnaviv_vram_mapping *mapping, u64 va);
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void etnaviv_iommu_unmap_gem(struct etnaviv_iommu_context *context,
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struct etnaviv_vram_mapping *mapping);
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int etnaviv_iommu_get_suballoc_va(struct etnaviv_iommu_context *ctx,
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struct etnaviv_vram_mapping *mapping,
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u32 memory_base, dma_addr_t paddr,
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size_t size);
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void etnaviv_iommu_put_suballoc_va(struct etnaviv_iommu_context *ctx,
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struct etnaviv_vram_mapping *mapping);
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size_t etnaviv_iommu_dump_size(struct etnaviv_iommu_context *ctx);
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void etnaviv_iommu_dump(struct etnaviv_iommu_context *ctx, void *buf);
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struct etnaviv_iommu_context *
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etnaviv_iommu_context_init(struct etnaviv_iommu_global *global,
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struct etnaviv_cmdbuf_suballoc *suballoc);
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static inline struct etnaviv_iommu_context *
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etnaviv_iommu_context_get(struct etnaviv_iommu_context *ctx)
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{
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kref_get(&ctx->refcount);
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return ctx;
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}
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void etnaviv_iommu_context_put(struct etnaviv_iommu_context *ctx);
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void etnaviv_iommu_restore(struct etnaviv_gpu *gpu,
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struct etnaviv_iommu_context *ctx);
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struct etnaviv_iommu_context *
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etnaviv_iommuv1_context_alloc(struct etnaviv_iommu_global *global);
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struct etnaviv_iommu_context *
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etnaviv_iommuv2_context_alloc(struct etnaviv_iommu_global *global);
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u32 etnaviv_iommuv2_get_mtlb_addr(struct etnaviv_iommu_context *context);
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unsigned short etnaviv_iommuv2_get_pta_id(struct etnaviv_iommu_context *context);
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#endif /* __ETNAVIV_MMU_H__ */
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