// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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#include "armada-385-clearfog-gtr.dtsi"
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/ {
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model = "SolidRun Clearfog GTR L8";
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};
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&mdio {
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switch0: switch0@4 {
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compatible = "marvell,mv88e6190";
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reg = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&cf_gtr_switch_reset_pins>;
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reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "lan8";
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phy-handle = <&switch0phy0>;
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};
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port@2 {
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reg = <2>;
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label = "lan7";
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phy-handle = <&switch0phy1>;
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};
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port@3 {
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reg = <3>;
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label = "lan6";
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phy-handle = <&switch0phy2>;
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};
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port@4 {
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reg = <4>;
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label = "lan5";
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phy-handle = <&switch0phy3>;
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};
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port@5 {
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reg = <5>;
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label = "lan4";
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phy-handle = <&switch0phy4>;
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};
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port@6 {
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reg = <6>;
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label = "lan3";
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phy-handle = <&switch0phy5>;
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};
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port@7 {
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reg = <7>;
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label = "lan2";
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phy-handle = <&switch0phy6>;
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};
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port@8 {
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reg = <8>;
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label = "lan1";
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phy-handle = <&switch0phy7>;
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};
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port@10 {
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reg = <10>;
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label = "cpu";
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ethernet = <ð1>;
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};
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};
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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switch0phy0: switch0phy0@1 {
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reg = <0x1>;
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};
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switch0phy1: switch0phy1@2 {
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reg = <0x2>;
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};
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switch0phy2: switch0phy2@3 {
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reg = <0x3>;
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};
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switch0phy3: switch0phy3@4 {
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reg = <0x4>;
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};
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switch0phy4: switch0phy4@5 {
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reg = <0x5>;
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};
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switch0phy5: switch0phy5@6 {
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reg = <0x6>;
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};
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switch0phy6: switch0phy6@7 {
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reg = <0x7>;
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};
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switch0phy7: switch0phy7@8 {
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reg = <0x8>;
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};
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};
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};
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};
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