Binding for MTK SPI Slave controller
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Required properties:
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- compatible: should be one of the following.
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- mediatek,mt2712-spi-slave: for mt2712 platforms
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- reg: Address and length of the register set for the device.
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- interrupts: Should contain spi interrupt.
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- clocks: phandles to input clocks.
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It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
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- clock-names: should be "spi" for the clock gate.
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Optional properties:
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- assigned-clocks: it's mux clock, should be <&topckgen CLK_TOP_SPISLV_SEL>.
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- assigned-clock-parents: parent of mux clock.
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It's PLL, and should be one of the following.
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- <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
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It's the default one.
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- <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
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- <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
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- <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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Example:
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- SoC Specific Portion:
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spis1: spi@10013000 {
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compatible = "mediatek,mt2712-spi-slave";
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reg = <0 0x10013000 0 0x100>;
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interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&infracfg CLK_INFRA_AO_SPI1>;
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clock-names = "spi";
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assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>;
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};
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